FirstInst = I;
continue;
}
- assert(isVectorLikeInstWithConstOps(FirstInst) &&
- isVectorLikeInstWithConstOps(I) &&
- "Expected vector-like insts only.");
+ assert((E->getOpcode() == Instruction::GetElementPtr &&
+ !isa<GetElementPtrInst>(I)) ||
+ (isVectorLikeInstWithConstOps(FirstInst) &&
+ isVectorLikeInstWithConstOps(I)) &&
+ "Expected vector-like or non-GEP in GEP node insts only.");
if (!DT->isReachableFromEntry(FirstInst->getParent())) {
FirstInst = I;
continue;
--- /dev/null
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
+; RUN: opt -passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -mcpu=skx -S < %s | FileCheck %s
+
+define void @test() {
+; CHECK-LABEL: define void @test
+; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[COND_IN_V:%.*]] = select i1 false, ptr null, ptr null
+; CHECK-NEXT: br label [[BB:%.*]]
+; CHECK: bb:
+; CHECK-NEXT: [[V:%.*]] = load i64, ptr [[COND_IN_V]], align 8
+; CHECK-NEXT: [[BV:%.*]] = icmp eq i64 [[V]], 0
+; CHECK-NEXT: [[IN_1:%.*]] = getelementptr i64, ptr [[COND_IN_V]], i64 4
+; CHECK-NEXT: [[V_1:%.*]] = load i64, ptr [[IN_1]], align 8
+; CHECK-NEXT: [[BV_1:%.*]] = icmp eq i64 [[V_1]], 0
+; CHECK-NEXT: [[IN_2:%.*]] = getelementptr i64, ptr [[COND_IN_V]], i64 8
+; CHECK-NEXT: [[V_2:%.*]] = load i64, ptr [[IN_2]], align 8
+; CHECK-NEXT: [[BV_2:%.*]] = icmp eq i64 [[V_2]], 0
+; CHECK-NEXT: [[IN_3:%.*]] = getelementptr i64, ptr [[COND_IN_V]], i64 12
+; CHECK-NEXT: [[V_3:%.*]] = load i64, ptr [[IN_3]], align 8
+; CHECK-NEXT: [[BV_3:%.*]] = icmp eq i64 [[V_3]], 0
+; CHECK-NEXT: ret void
+;
+entry:
+ %cond.in.v = select i1 false, ptr null, ptr null
+ br label %bb
+
+bb: ; preds = %entry
+ %v = load i64, ptr %cond.in.v, align 8
+ %bv = icmp eq i64 %v, 0
+ %in.1 = getelementptr i64, ptr %cond.in.v, i64 4
+ %v.1 = load i64, ptr %in.1, align 8
+ %bv.1 = icmp eq i64 %v.1, 0
+ %in.2 = getelementptr i64, ptr %cond.in.v, i64 8
+ %v.2 = load i64, ptr %in.2, align 8
+ %bv.2 = icmp eq i64 %v.2, 0
+ %in.3 = getelementptr i64, ptr %cond.in.v, i64 12
+ %v.3 = load i64, ptr %in.3, align 8
+ %bv.3 = icmp eq i64 %v.3, 0
+ ret void
+}