MIPS: Loongson64: DeviceTree for Loongson-2K1000

Add DeviceTree files for Loongson-2K1000 processor, currently only
supports single-core boot.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Qing Zhang <zhangqing@loongson.cn>
Tested-by: Ming Wang <wangming01@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile
index 8fd0efb..72267bf 100644 (file)
--- a/arch/mips/boot/dts/loongson/Makefile
+++ b/arch/mips/boot/dts/loongson/Makefile
@@ -1,4 +1,5 @@
 # SPDX_License_Identifier: GPL_2.0
+dtb-$(CONFIG_MACH_LOONGSON64)  += loongson64_2core_2k1000.dtb
 dtb-$(CONFIG_MACH_LOONGSON64)  += loongson64c_4core_ls7a.dtb
 dtb-$(CONFIG_MACH_LOONGSON64)  += loongson64c_4core_rs780e.dtb
 dtb-$(CONFIG_MACH_LOONGSON64)  += loongson64c_8core_rs780e.dtb

diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
new file mode 100644 (file)
index 0000000..fd0e99b
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: GPL-3.0
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+       compatible = "loongson,loongson2k1000";
+
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "loongson,gs264";
+                       reg = <0x0>;
+                       #clock-cells = <1>;
+                       clocks = <&cpu_clk>;
+               };
+       };
+
+       memory {
+               compatible = "memory";
+               device_type = "memory";
+               reg = <0x00000000 0x00200000 0x00000000 0x0ee00000>, /* 238 MB at 2 MB */
+                       <0x00000000 0x20000000 0x00000000 0x1f000000>, /* 496 MB at 512 MB */
+                       <0x00000001 0x10000000 0x00000001 0xb0000000>; /* 6912 MB at 4352MB */
+       };
+
+       cpu_clk: cpu_clk {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <800000000>;
+       };
+
+       cpuintc: interrupt-controller {
+               #address-cells = <0>;
+               #interrupt-cells = <1>;
+               interrupt-controller;
+               compatible = "mti,cpu-interrupt-controller";
+       };
+
+       package0: bus@10000000 {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* ioports */
+                       0 0x40000000 0 0x40000000 0 0x40000000
+                       0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;
+
+               liointc0: interrupt-controller@1fe11400 {
+                       compatible = "loongson,liointc-2.0";
+                       reg = <0 0x1fe11400 0 0x40>,
+                               <0 0x1fe11040 0 0x8>,
+                               <0 0x1fe11140 0 0x8>;
+                       reg-names = "main", "isr0", "isr1";
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&cpuintc>;
+                       interrupts = <2>;
+                       interrupt-names = "int0";
+
+                       loongson,parent_int_map = <0xffffffff>, /* int0 */
+                                               <0x00000000>, /* int1 */
+                                               <0x00000000>, /* int2 */
+                                               <0x00000000>; /* int3 */
+               };
+
+               liointc1: interrupt-controller@1fe11440 {
+                       compatible = "loongson,liointc-2.0";
+                       reg = <0 0x1fe11440 0 0x40>,
+                               <0 0x1fe11048 0 0x8>,
+                               <0 0x1fe11148 0 0x8>;
+                       reg-names = "main", "isr0", "isr1";
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&cpuintc>;
+                       interrupts = <3>;
+                       interrupt-names = "int1";
+
+                       loongson,parent_int_map = <0x00000000>, /* int0 */
+                                               <0xffffffff>, /* int1 */
+                                               <0x00000000>, /* int2 */
+                                               <0x00000000>; /* int3 */
+               };
+
+               uart0: serial@1fe00000 {
+                       compatible = "ns16550a";
+                       reg = <0 0x1fe00000 0 0x8>;
+                       clock-frequency = <125000000>;
+                       interrupt-parent = <&liointc0>;
+                       interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+                       no-loopback-test;
+               };
+
+               pci@1a000000 {
+                       compatible = "loongson,ls2k-pci";
+                       device_type = "pci";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <2>;
+
+                       reg = <0 0x1a000000 0 0x02000000>,
+                               <0xfe 0x00000000 0 0x20000000>;
+
+                       ranges = <0x01000000 0x0 0x00000000 0x0 0x18000000  0x0 0x00010000>,
+                                <0x02000000 0x0 0x40000000 0x0 0x40000000  0x0 0x40000000>;
+
+                       ehci@4,1 {
+                               compatible = "pci0014,7a14.0",
+                                                  "pci0014,7a14",
+                                                  "pciclass0c0320",
+                                                  "pciclass0c03";
+
+                               reg = <0x2100 0x0 0x0 0x0 0x0>;
+                               interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+                               interrupt-parent = <&liointc1>;
+                       };
+
+                       ehci@4,2 {
+                               compatible = "pci0014,7a24.0",
+                                                  "pci0014,7a24",
+                                                  "pciclass0c0310",
+                                                  "pciclass0c03";
+
+                               reg = <0x2200 0x0 0x0 0x0 0x0>;
+                               interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+                               interrupt-parent = <&liointc1>;
+                       };
+
+                       sata@8,0 {
+                               compatible = "pci0014,7a08.0",
+                                                  "pci0014,7a08",
+                                                  "pciclass010601",
+                                                  "pciclass0106";
+
+                               reg = <0x4000 0x0 0x0 0x0 0x0>;
+                               interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+                               interrupt-parent = <&liointc0>;
+                       };
+
+                       pci_bridge@9,0 {
+                               compatible = "pci0014,7a19.0",
+                                                  "pci0014,7a19",
+                                                  "pciclass060400",
+                                                  "pciclass0604";
+
+                               reg = <0x4800 0x0 0x0 0x0 0x0>;
+                               #interrupt-cells = <1>;
+                               interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+                               interrupt-parent = <&liointc1>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_LOW>;
+                               external-facing;
+                       };
+
+                       pci_bridge@a,0 {
+                               compatible = "pci0014,7a19.0",
+                                                  "pci0014,7a19",
+                                                  "pciclass060400",
+                                                  "pciclass0604";
+
+                               reg = <0x5000 0x0 0x0 0x0 0x0>;
+                               #interrupt-cells = <1>;
+                               interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+                               interrupt-parent = <&liointc1>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_LOW>;
+                               external-facing;
+                       };
+
+                       pci_bridge@b,0 {
+                               compatible = "pci0014,7a19.0",
+                                                  "pci0014,7a19",
+                                                  "pciclass060400",
+                                                  "pciclass0604";
+
+                               reg = <0x5800 0x0 0x0 0x0 0x0>;
+                               #interrupt-cells = <1>;
+                               interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+                               interrupt-parent = <&liointc1>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_LOW>;
+                               external-facing;
+                       };
+
+                       pci_bridge@c,0 {
+                               compatible = "pci0014,7a19.0",
+                                                  "pci0014,7a19",
+                                                  "pciclass060400",
+                                                  "pciclass0604";
+
+                               reg = <0x6000 0x0 0x0 0x0 0x0>;
+                               #interrupt-cells = <1>;
+                               interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+                               interrupt-parent = <&liointc1>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_LOW>;
+                               external-facing;
+                       };
+
+                       pci_bridge@d,0 {
+                               compatible = "pci0014,7a19.0",
+                                                  "pci0014,7a19",
+                                                  "pciclass060400",
+                                                  "pciclass0604";
+
+                               reg = <0x6800 0x0 0x0 0x0 0x0>;
+                               #interrupt-cells = <1>;
+                               interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+                               interrupt-parent = <&liointc1>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_LOW>;
+                               external-facing;
+                       };
+
+                       pci_bridge@e,0 {
+                               compatible = "pci0014,7a19.0",
+                                                  "pci0014,7a19",
+                                                  "pciclass060400",
+                                                  "pciclass0604";
+
+                               reg = <0x7000 0x0 0x0 0x0 0x0>;
+                               #interrupt-cells = <1>;
+                               interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+                               interrupt-parent = <&liointc1>;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_LOW>;
+                               external-facing;
+                       };
+
+               };
+       };
+};
+

diff --git a/arch/mips/boot/dts/loongson/loongson64_2core_2k1000.dts b/arch/mips/boot/dts/loongson/loongson64_2core_2k1000.dts
new file mode 100644 (file)
index 0000000..e31d2ee
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson64_2core_2k1000.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson64-2k1000.dtsi"
+
+/ {
+       compatible = "loongson,loongson64-2core-2k1000";
+};
+

diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
index 839410c..8be7105 100644 (file)
--- a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
+++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
@@ -8,6 +8,7 @@
 #ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
 #define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
 
+extern u32 __dtb_loongson64_2core_2k1000_begin[];
 extern u32 __dtb_loongson64c_4core_ls7a_begin[];
 extern u32 __dtb_loongson64c_4core_rs780e_begin[];
 extern u32 __dtb_loongson64c_8core_rs780e_begin[];