[S5PC100] add ONENAND register in s5pc1xx.h

diff --git a/include/s5pc1xx.h b/include/s5pc1xx.h
index aae52a7..e7ef17b 100644 (file)
--- a/include/s5pc1xx.h
+++ b/include/s5pc1xx.h
@@ -1242,7 +1242,104 @@
 
 
 /* OneNand */
-
+#define S5P_ONENANDC_BASE(x)   (S5P_PA_ONENANDC + (x))
+
+#define MEM_CFG_OFFSET                 0x0
+#define BURST_LEN_OFFSET               0x10
+#define MEM_RESET_OFFSET               0x20
+#define INT_ERR_STAT_OFFSET            0x30
+#define INT_ERR_MASK_OFFSET            0x40
+#define INT_ERR_ACK_OFFSET             0x50
+#define ECC_ERR_STAT_1_OFFSET  0x60
+#define MANUFACT_ID_OFFSET             0x70
+#define DEVICE_ID_OFFSET               0x80
+#define DATA_BUF_SIZE_OFFSET   0x90
+#define BOOT_BUF_SIZE_OFFSET   0xa0
+#define BUF_AMOUNT_OFFSET              0xb0
+#define TECH_OFFSET                            0xc0
+#define FBA_WIDTH_OFFSET               0xd0
+#define FPA_WIDTH_OFFSET               0xe0
+#define FSA_WIDTH_OFFSET               0xf0
+#define REVISION_OFFSET                        0x100
+#define SYNC_MODE_OFFSET               0x130
+#define TRANS_SPARE_OFFSET             0x140
+#define PAGE_CNT_OFFSET                        0x170
+#define ERR_PAGE_ADDR_OFFSET   0x180
+#define BURST_RD_LAT_OFFSET            0x190
+#define INT_PIN_ENABLE_OFFSET  0x1a0
+#define INT_MON_CYC_OFFSET             0x1b0
+#define ACC_CLOCK_OFFSET               0x1c0
+#define ERR_BLK_ADDR_OFFSET            0x1e0
+#define FLASH_VER_ID_OFFSET            0x1f0
+#define BANK_EN_OFFSET                 0x220
+#define WTCHDG_RST_L_OFFSET            0x260
+#define WTCHDG_RST_H_OFFSET            0x270
+#define SYNC_WRITE_OFFSET              0x280
+#define CACHE_READ_OFFSET              0x290
+#define COLD_RST_DLY_OFFSET            0x2a0
+#define DDP_DEVICE_OFFSET              0x2b0
+#define MULTI_PLANE_OFFSET             0x2c0
+#define TRANS_MODE_OFFSET              0x2e0
+#define DEV_STAT_OFFSET                        0x2f0
+#define ECC_ERR_STAT_2_OFFSET  0x300
+#define ECC_ERR_STAT_3_OFFSET  0x310
+#define ECC_ERR_STAT_4_OFFSET  0x320
+#define EFCT_BUF_CNT_OFFSET            0x330
+#define DEV_PAGE_SIZE_OFFSET   0x340
+#define SUPERLOAD_EN_OFFSET            0x350
+#define CACHE_PRG_EN_OFFSET            0x360
+#define SINGLE_PAGE_BUF_OFFSET 0x370
+#define OFFSET_ADDR_OFFSET             0x380
+#define INT_MON_STATUS_OFFSET  0x390
+
+#define S5P_MEM_CFG                    S5P_ONENANDC_BASE(MEM_CFG_OFFSET)
+#define S5P_BURST_LEN          S5P_ONENANDC_BASE(BURST_LEN_OFFSET)
+#define S5P_MEM_RESET          S5P_ONENANDC_BASE(MEM_RESET_OFFSET)
+#define S5P_INT_ERR_STAT       S5P_ONENANDC_BASE(INT_ERR_STAT_OFFSET)
+#define S5P_INT_ERR_MASK       S5P_ONENANDC_BASE(INT_ERR_MASK_OFFSET)
+#define S5P_INT_ERR_ACK                S5P_ONENANDC_BASE(INT_ERR_ACK_OFFSET)
+#define S5P_ECC_ERR_STAT_1     S5P_ONENANDC_BASE(ECC_ERR_STAT_1_OFFSET)
+#define S5P_MANUFACT_ID                S5P_ONENANDC_BASE(MANUFACT_ID_OFFSET)
+#define S5P_DEVICE_ID          S5P_ONENANDC_BASE(DEVICE_ID_OFFSET)
+#define S5P_DATA_BUF_SIZE      S5P_ONENANDC_BASE(DATA_BUF_SIZE_OFFSET)
+#define S5P_BOOT_BUF_SIZE      S5P_ONENANDC_BASE(BOOT_BUF_SIZE_OFFSET)
+#define S5P_BUF_AMOUNT         S5P_ONENANDC_BASE(BUF_AMOUNT_OFFSET)
+#define S5P_TECH                       S5P_ONENANDC_BASE(TECH_OFFSET)
+#define S5P_FBA_WIDTH          S5P_ONENANDC_BASE(FBA_WIDTH_OFFSET)
+#define S5P_FPA_WIDTH          S5P_ONENANDC_BASE(FPA_WIDTH_OFFSET)
+#define S5P_FSA_WIDTH          S5P_ONENANDC_BASE(FSA_WIDTH_OFFSET)
+#define S5P_REVISION           S5P_ONENANDC_BASE(REVISION_OFFSET)
+#define S5P_SYNC_MODE          S5P_ONENANDC_BASE(SYNC_MODE_OFFSET)
+#define S5P_TRANS_SPARE                S5P_ONENANDC_BASE(TRANS_SPARE_OFFSET)
+#define S5P_PAGE_CNT           S5P_ONENANDC_BASE(PAGE_CNT_OFFSET)
+#define S5P_ERR_PAGE_ADDR      S5P_ONENANDC_BASE(ERR_PAGE_ADDR_OFFSET)
+#define S5P_BURST_RD_LAT       S5P_ONENANDC_BASE(BURST_RD_LAT_OFFSET)
+#define S5P_INT_PIN_ENABLE     S5P_ONENANDC_BASE(INT_PIN_ENABLE_OFFSET)
+#define S5P_INT_MON_CYC                S5P_ONENANDC_BASE(INT_MON_CYC_OFFSET)
+#define S5P_ACC_CLOCK          S5P_ONENANDC_BASE(ACC_CLOCK_OFFSET)
+#define S5P_ERR_BLK_ADDR       S5P_ONENANDC_BASE(ERR_BLK_ADDR_OFFSET)
+#define S5P_FLASH_VER_ID       S5P_ONENANDC_BASE(FLASH_VER_ID_OFFSET)
+#define S5P_BANK_EN                    S5P_ONENANDC_BASE(BANK_EN_OFFSET)
+#define S5P_WTCHDG_RST_L       S5P_ONENANDC_BASE(WTCHDG_RST_L_OFFSET)
+#define S5P_WTCHDG_RST_H       S5P_ONENANDC_BASE(WTCHDG_RST_H_OFFSET)
+#define S5P_SYNC_WRITE         S5P_ONENANDC_BASE(SYNC_WRITE_OFFSET)
+#define S5P_CACHE_READ         S5P_ONENANDC_BASE(CACHE_READ_OFFSET)
+#define S5P_COLD_RST_DLY       S5P_ONENANDC_BASE(COLD_RST_DLY_OFFSET)
+#define S5P_DDP_DEVICE         S5P_ONENANDC_BASE(DDP_DEVICE_OFFSET)
+#define S5P_MULTI_PLANE                S5P_ONENANDC_BASE(MULTI_PLANE_OFFSET)
+#define S5P_MEM_CNT                    S5P_ONENANDC_BASE(MEM_CNT_OFFSET)
+#define S5P_TRANS_MODE         S5P_ONENANDC_BASE(TRANS_MODE_OFFSET)
+#define S5P_DEV_START          S5P_ONENANDC_BASE(DEV_START_OFFSET)
+#define S5P_ECC_ERR_STAT_2     S5P_ONENANDC_BASE(ECC_ERR_STAT_2_OFFSET)
+#define S5P_ECC_ERR_STAT_3     S5P_ONENANDC_BASE(ECC_ERR_STAT_3_OFFSET)
+#define S5P_ECC_ERR_STAT_4     S5P_ONENANDC_BASE(ECC_ERR_STAT_4_OFFSET)
+#define S5P_EFCT_BUF_CNT       S5P_ONENANDC_BASE(EFCT_BUF_CNT_OFFSET)
+#define S5P_DEV_PAGE_SIZE      S5P_ONENANDC_BASE(DEV_PAGE_SIZE_OFFSET)
+#define S5P_SUPERLOAD_EN       S5P_ONENANDC_BASE(SUPERLOAD_EN_OFFSET)
+#define S5P_CACHE_PRG_EN       S5P_ONENANDC_BASE(CACHE_PRG_EN_OFFSET)
+#define S5P_SINGLE_PAGE_BUF    S5P_ONENANDC_BASE(SINGLE_PAGE_BUF_OFFSET)
+#define S5P_OFFSET_ADDR                S5P_ONENANDC_BASE(OFFSET_ADDR_OFFSET)
+#define S5P_INT_MON_STATUS     S5P_ONENANDC_BASE(INT_MON_STATUS_OFFSET)