net/mlx5: Lag, enable hash mode by default for all NICs

The firmware supports adding a steering rule to catch egress traffic
of the QPs/TISs which are set port affinity explicitly in hash mode.
Enable that mode for NICS with 2 ports as well.

Signed-off-by: Liu, Changcheng <jerrliu@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c
index 90d3054..a9f4ede 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c
@@ -484,21 +484,22 @@ void mlx5_modify_lag(struct mlx5_lag *ldev,
                mlx5_lag_drop_rule_setup(ldev, tracker);
 }
 
-#define MLX5_LAG_ROCE_HASH_PORTS_SUPPORTED 4
 static int mlx5_lag_set_port_sel_mode_roce(struct mlx5_lag *ldev,
                                           unsigned long *flags)
 {
-       struct lag_func *dev0 = &ldev->pf[MLX5_LAG_P1];
+       struct mlx5_core_dev *dev0 = ldev->pf[MLX5_LAG_P1].dev;
 
-       if (ldev->ports == MLX5_LAG_ROCE_HASH_PORTS_SUPPORTED) {
-               /* Four ports are support only in hash mode */
-               if (!MLX5_CAP_PORT_SELECTION(dev0->dev, port_select_flow_table))
-                       return -EINVAL;
-               set_bit(MLX5_LAG_MODE_FLAG_HASH_BASED, flags);
+       if (!MLX5_CAP_PORT_SELECTION(dev0, port_select_flow_table)) {
                if (ldev->ports > 2)
-                       ldev->buckets = MLX5_LAG_MAX_HASH_BUCKETS;
+                       return -EINVAL;
+               return 0;
        }
 
+       if (ldev->ports > 2)
+               ldev->buckets = MLX5_LAG_MAX_HASH_BUCKETS;
+
+       set_bit(MLX5_LAG_MODE_FLAG_HASH_BASED, flags);
+
        return 0;
 }