dt-bindings/bcm283x: Define polarity of per-cpu interrupts
authorStefan Wahren <stefan.wahren@i2se.com>
Mon, 11 Dec 2017 20:39:12 +0000 (21:39 +0100)
committerMarc Zyngier <marc.zyngier@arm.com>
Thu, 4 Jan 2018 11:12:46 +0000 (11:12 +0000)
This patch define the polarity of the per-cpu interrupts on BCM2836
and BCM2837 in order to avoid the warnings from ARM arch timer code:

    arch_timer: WARNING: Invalid trigger for IRQ19, assuming level low
    arch_timer: WARNING: Please fix your firmware
    arch_timer: cp15 timer(s) running at 19.20MHz (virt).

Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
arch/arm/boot/dts/bcm2836.dtsi
arch/arm/boot/dts/bcm2837.dtsi
arch/arm/boot/dts/bcm283x.dtsi

index 61e1580035097017f37b9b8e660e2f3b829f9d4b..1dfd7644277736fb58fa4ad8352091677a000d5e 100644 (file)
                        compatible = "brcm,bcm2836-l1-intc";
                        reg = <0x40000000 0x100>;
                        interrupt-controller;
-                       #interrupt-cells = <1>;
+                       #interrupt-cells = <2>;
                        interrupt-parent = <&local_intc>;
                };
 
                arm-pmu {
                        compatible = "arm,cortex-a7-pmu";
                        interrupt-parent = <&local_intc>;
-                       interrupts = <9>;
+                       interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
                };
        };
 
        timer {
                compatible = "arm,armv7-timer";
                interrupt-parent = <&local_intc>;
-               interrupts = <0>, // PHYS_SECURE_PPI
-                            <1>, // PHYS_NONSECURE_PPI
-                            <3>, // VIRT_PPI
-                            <2>; // HYP_PPI
+               interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
+                            <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
+                            <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
+                            <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
                always-on;
        };
 
@@ -76,7 +76,7 @@
        compatible = "brcm,bcm2836-armctrl-ic";
        reg = <0x7e00b200 0x200>;
        interrupt-parent = <&local_intc>;
-       interrupts = <8>;
+       interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
 };
 
 &cpu_thermal {
index bc1cca5cf43c41b8dad3902ce1a627b625883cb3..efa7d3387ab287fb72e66659644a36903c85e5fc 100644 (file)
@@ -12,7 +12,7 @@
                        compatible = "brcm,bcm2836-l1-intc";
                        reg = <0x40000000 0x100>;
                        interrupt-controller;
-                       #interrupt-cells = <1>;
+                       #interrupt-cells = <2>;
                        interrupt-parent = <&local_intc>;
                };
        };
        timer {
                compatible = "arm,armv7-timer";
                interrupt-parent = <&local_intc>;
-               interrupts = <0>, // PHYS_SECURE_PPI
-                            <1>, // PHYS_NONSECURE_PPI
-                            <3>, // VIRT_PPI
-                            <2>; // HYP_PPI
+               interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
+                            <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
+                            <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
+                            <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
                always-on;
        };
 
@@ -73,7 +73,7 @@
        compatible = "brcm,bcm2836-armctrl-ic";
        reg = <0x7e00b200 0x200>;
        interrupt-parent = <&local_intc>;
-       interrupts = <8>;
+       interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
 };
 
 &cpu_thermal {
index dcde93c85c2d38e0f230ca21c700cb7755d9ec55..18db25a5a66e0c1685457cd7959bdf239db5c76c 100644 (file)
@@ -2,6 +2,7 @@
 #include <dt-bindings/clock/bcm2835.h>
 #include <dt-bindings/clock/bcm2835-aux.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 /* firmware-provided startup stubs live here, where the secondary CPUs are
  * spinning.