Known = KnownBits::ashr(Known, Known2);
break;
}
+ case AArch64ISD::MOVI: {
+ ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(0));
+ Known =
+ KnownBits::makeConstant(APInt(Known.getBitWidth(), CN->getZExtValue()));
+ break;
+ }
case AArch64ISD::LOADgot:
case AArch64ISD::ADDlow: {
if (!Subtarget->isTargetILP32())
bool AArch64TargetLowering::isTargetCanonicalConstantNode(SDValue Op) const {
return Op.getOpcode() == AArch64ISD::DUP ||
+ Op.getOpcode() == AArch64ISD::MOVI ||
(Op.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
Op.getOperand(0).getOpcode() == AArch64ISD::DUP) ||
TargetLowering::isTargetCanonicalConstantNode(Op);
; CHECK-NEXT: movi v2.16b, #1
; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: ushr v1.8h, v0.8h, #7
-; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: usra v0.8h, v0.8h, #7
; CHECK-NEXT: ret
%3 = icmp eq <16 x i8> %0, %1
%4 = zext <16 x i1> %3 to <16 x i8>
; CHECK-NEXT: movi v2.16b, #1
; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: ushr v1.4s, v0.4s, #15
-; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: usra v0.4s, v0.4s, #15
; CHECK-NEXT: ret
%3 = icmp eq <16 x i8> %0, %1
%4 = zext <16 x i1> %3 to <16 x i8>
; CHECK-NEXT: movi v2.16b, #1
; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: ushr v1.2d, v0.2d, #31
-; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: usra v0.2d, v0.2d, #31
; CHECK-NEXT: ret
%3 = icmp eq <16 x i8> %0, %1
%4 = zext <16 x i1> %3 to <16 x i8>