enum anv_pipe_bits
genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
struct anv_device *device,
- uint32_t current_pipeline,
+ enum anv_hw_pipeline_state current_pipeline,
enum anv_pipe_bits bits);
void genX(emit_so_memcpy_init)(struct anv_memcpy_state *state,
VkResult
anv_pipeline_init(struct anv_pipeline *pipeline,
struct anv_device *device,
- enum anv_pipeline_type type,
+ enum anv_hw_pipeline_state type,
VkPipelineCreateFlags flags,
const VkAllocationCallbacks *pAllocator)
{
return;
switch (pipeline->type) {
- case ANV_PIPELINE_GRAPHICS: {
+ case ANV_HW_PIPELINE_STATE_GRAPHICS: {
struct anv_graphics_pipeline *gfx_pipeline =
anv_pipeline_to_graphics(pipeline);
break;
}
- case ANV_PIPELINE_COMPUTE: {
+ case ANV_HW_PIPELINE_STATE_COMPUTE: {
struct anv_compute_pipeline *compute_pipeline =
anv_pipeline_to_compute(pipeline);
break;
}
- case ANV_PIPELINE_RAY_TRACING: {
+ case ANV_HW_PIPELINE_STATE_RAY_TRACING: {
struct anv_ray_tracing_pipeline *rt_pipeline =
anv_pipeline_to_ray_tracing(pipeline);
NIR_PASS(_, nir, anv_nir_lower_ycbcr_textures, layout);
- if (pipeline->type == ANV_PIPELINE_GRAPHICS) {
+ if (pipeline->type == ANV_HW_PIPELINE_STATE_GRAPHICS) {
struct anv_graphics_pipeline *gfx_pipeline =
anv_pipeline_to_graphics(pipeline);
NIR_PASS(_, nir, anv_nir_lower_multiview, gfx_pipeline->view_mask,
return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
result = anv_pipeline_init(&pipeline->base, device,
- ANV_PIPELINE_COMPUTE, pCreateInfo->flags,
+ ANV_HW_PIPELINE_STATE_COMPUTE, pCreateInfo->flags,
pAllocator);
if (result != VK_SUCCESS) {
vk_free2(&device->vk.alloc, pAllocator, pipeline);
VkResult result;
result = anv_pipeline_init(&pipeline->base, device,
- ANV_PIPELINE_GRAPHICS, pCreateInfo->flags,
+ ANV_HW_PIPELINE_STATE_GRAPHICS, pCreateInfo->flags,
alloc);
if (result != VK_SUCCESS)
return result;
return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
result = anv_pipeline_init(&pipeline->base, device,
- ANV_PIPELINE_RAY_TRACING, pCreateInfo->flags,
+ ANV_HW_PIPELINE_STATE_RAY_TRACING, pCreateInfo->flags,
pAllocator);
if (result != VK_SUCCESS) {
vk_free2(&device->vk.alloc, pAllocator, pipeline);
const struct brw_stage_prog_data *prog_data;
switch (pipeline->type) {
- case ANV_PIPELINE_GRAPHICS: {
+ case ANV_HW_PIPELINE_STATE_GRAPHICS: {
prog_data = anv_pipeline_to_graphics(pipeline)->shaders[exe->stage]->prog_data;
break;
}
- case ANV_PIPELINE_COMPUTE: {
+ case ANV_HW_PIPELINE_STATE_COMPUTE: {
prog_data = anv_pipeline_to_compute(pipeline)->cs->prog_data;
break;
}
- case ANV_PIPELINE_RAY_TRACING: {
+ case ANV_HW_PIPELINE_STATE_RAY_TRACING: {
struct anv_shader_bin **shader =
util_dynarray_element(&anv_pipeline_to_ray_tracing(pipeline)->shaders,
struct anv_shader_bin *,
ANV_FROM_HANDLE(anv_device, device, _device);
ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
- if (pipeline->type != ANV_PIPELINE_RAY_TRACING)
+ if (pipeline->type != ANV_HW_PIPELINE_STATE_RAY_TRACING)
return vk_error(device, VK_ERROR_FEATURE_NOT_PRESENT);
struct anv_ray_tracing_pipeline *rt_pipeline =
VkShaderGroupShaderKHR groupShader)
{
ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
- assert(pipeline->type == ANV_PIPELINE_RAY_TRACING);
+ assert(pipeline->type == ANV_HW_PIPELINE_STATE_RAY_TRACING);
struct anv_ray_tracing_pipeline *rt_pipeline =
anv_pipeline_to_ray_tracing(pipeline);
} scratch;
};
+enum anv_hw_pipeline_state {
+ ANV_HW_PIPELINE_STATE_GRAPHICS,
+ ANV_HW_PIPELINE_STATE_COMPUTE,
+ ANV_HW_PIPELINE_STATE_RAY_TRACING,
+};
+
/** State required while building cmd buffer */
struct anv_cmd_state {
- /* PIPELINE_SELECT.PipelineSelection */
- uint32_t current_pipeline;
+ enum anv_hw_pipeline_state current_pipeline;
const struct intel_l3_config * current_l3_config;
uint32_t last_aux_map_state;
char *disasm;
};
-enum anv_pipeline_type {
- ANV_PIPELINE_GRAPHICS,
- ANV_PIPELINE_COMPUTE,
- ANV_PIPELINE_RAY_TRACING,
-};
-
struct anv_pipeline {
struct vk_object_base base;
void * mem_ctx;
- enum anv_pipeline_type type;
+ enum anv_hw_pipeline_state type;
VkPipelineCreateFlags flags;
uint32_t ray_queries;
return (struct anv_##pipe_type##_pipeline *) pipeline; \
}
-ANV_DECL_PIPELINE_DOWNCAST(graphics, ANV_PIPELINE_GRAPHICS)
-ANV_DECL_PIPELINE_DOWNCAST(compute, ANV_PIPELINE_COMPUTE)
-ANV_DECL_PIPELINE_DOWNCAST(ray_tracing, ANV_PIPELINE_RAY_TRACING)
+ANV_DECL_PIPELINE_DOWNCAST(graphics, ANV_HW_PIPELINE_STATE_GRAPHICS)
+ANV_DECL_PIPELINE_DOWNCAST(compute, ANV_HW_PIPELINE_STATE_COMPUTE)
+ANV_DECL_PIPELINE_DOWNCAST(ray_tracing, ANV_HW_PIPELINE_STATE_RAY_TRACING)
static inline bool
anv_pipeline_has_stage(const struct anv_graphics_pipeline *pipeline,
VkResult
anv_pipeline_init(struct anv_pipeline *pipeline,
struct anv_device *device,
- enum anv_pipeline_type type,
+ enum anv_hw_pipeline_state type,
VkPipelineCreateFlags flags,
const VkAllocationCallbacks *pAllocator);
#include "genX_cmd_draw_helpers.h"
static void genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
- uint32_t pipeline);
+ enum anv_hw_pipeline_state pipeline);
static enum anv_pipe_bits
convert_pc_to_bits(struct GENX(PIPE_CONTROL) *pc) {
* Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
* mode by putting the pipeline temporarily in 3D mode.
*/
- uint32_t gfx12_wa_pipeline = cmd_buffer->state.current_pipeline;
+ enum anv_hw_pipeline_state gfx12_wa_pipeline =
+ cmd_buffer->state.current_pipeline;
genX(flush_pipeline_select_3d)(cmd_buffer);
#endif
ALWAYS_INLINE enum anv_pipe_bits
genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
struct anv_device *device,
- uint32_t current_pipeline,
+ enum anv_hw_pipeline_state current_pipeline,
enum anv_pipe_bits bits)
{
#if GFX_VER >= 12
* The same text exists a few rows below for Post Sync Op.
*/
if (bits & ANV_PIPE_POST_SYNC_BIT) {
- if (GFX_VER == 9 && current_pipeline == GPGPU)
+ if (GFX_VER == 9 && current_pipeline == ANV_HW_PIPELINE_STATE_COMPUTE)
bits |= ANV_PIPE_CS_STALL_BIT;
bits &= ~ANV_PIPE_POST_SYNC_BIT;
}
#endif /* GFX_VERx10 >= 125 */
+static uint32_t
+anv_pipeline_selection_from_type(enum anv_hw_pipeline_state pipeline)
+{
+ switch (pipeline) {
+ case ANV_HW_PIPELINE_STATE_GRAPHICS:
+ return _3D;
+ case ANV_HW_PIPELINE_STATE_COMPUTE:
+ case ANV_HW_PIPELINE_STATE_RAY_TRACING:
+ return GPGPU;
+ default:
+ unreachable("Unsupported pipeline");
+ }
+}
+
static void
genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
- uint32_t pipeline)
+ enum anv_hw_pipeline_state pipeline)
{
UNUSED const struct intel_device_info *devinfo = cmd_buffer->device->info;
* The internal hardware docs recommend the same workaround for Gfx9
* hardware too.
*/
- if (pipeline == GPGPU)
+ if (pipeline == ANV_HW_PIPELINE_STATE_COMPUTE)
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), t);
- if (pipeline == _3D) {
+ if (pipeline == ANV_HW_PIPELINE_STATE_GRAPHICS) {
/* There is a mid-object preemption workaround which requires you to
* re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
* even without preemption, we have issues with geometry flickering when
anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) {
ps.MaskBits = GFX_VER >= 12 ? 0x13 : 3;
ps.MediaSamplerDOPClockGateEnable = GFX_VER >= 12;
- ps.PipelineSelection = pipeline;
+ ps.PipelineSelection = anv_pipeline_selection_from_type(pipeline);
}
#if GFX_VER == 9
void
genX(flush_pipeline_select_3d)(struct anv_cmd_buffer *cmd_buffer)
{
- genX(flush_pipeline_select)(cmd_buffer, _3D);
+ genX(flush_pipeline_select)(cmd_buffer, ANV_HW_PIPELINE_STATE_GRAPHICS);
}
void
genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer *cmd_buffer)
{
- genX(flush_pipeline_select)(cmd_buffer, GPGPU);
+ genX(flush_pipeline_select)(cmd_buffer, ANV_HW_PIPELINE_STATE_COMPUTE);
}
void
void
genX(emit_so_memcpy_fini)(struct anv_memcpy_state *state)
{
- genX(emit_apply_pipe_flushes)(state->batch, state->device, _3D,
+ genX(emit_apply_pipe_flushes)(state->batch, state->device,
+ ANV_HW_PIPELINE_STATE_GRAPHICS,
ANV_PIPE_END_OF_PIPE_SYNC_BIT);
anv_batch_emit(state->batch, GENX(MI_BATCH_BUFFER_END), end);
anv_gfx8_9_vb_cache_range_needs_workaround(&state->vb_bound,
&state->vb_dirty,
src, size)) {
- genX(emit_apply_pipe_flushes)(state->batch, state->device, _3D,
+ genX(emit_apply_pipe_flushes)(state->batch, state->device,
+ ANV_HW_PIPELINE_STATE_GRAPHICS,
ANV_PIPE_CS_STALL_BIT |
ANV_PIPE_VF_CACHE_INVALIDATE_BIT);
memset(&state->vb_dirty, 0, sizeof(state->vb_dirty));