arm64: dts: qcom: sm6375: Add QUPs and corresponding SPI/I2C hosts

Add necessary nodes to support various QUP configurations. Note that:

- QUP3/4/5 and 11 are straight up missing
- There may be more QUPs physically on the SoC that work perfectly
fine, but Qualcomm decided not to expose them on the downstream kernel
- Many are missing pinctrls, as there are both missing pin funcs in
the TLMM driver and missing configuration settings (though they are
possible to guesstimate quite easily)

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115152727.9736-6-konrad.dybcio@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
index 9521568..6adffd9 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6375.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/clock/qcom,rpmcc.h>
 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
+#include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
@@ -317,6 +318,25 @@
                };
        };
 
+       qup_opp_table: opp-table-qup {
+               compatible = "operating-points-v2";
+
+               opp-75000000 {
+                       opp-hz = /bits/ 64 <75000000>;
+                       required-opps = <&rpmpd_opp_low_svs>;
+               };
+
+               opp-100000000 {
+                       opp-hz = /bits/ 64 <100000000>;
+                       required-opps = <&rpmpd_opp_svs>;
+               };
+
+               opp-128000000 {
+                       opp-hz = /bits/ 64 <128000000>;
+                       required-opps = <&rpmpd_opp_nom>;
+               };
+       };
+
        reserved_memory: reserved-memory {
                #address-cells = <2>;
                #size-cells = <2>;
@@ -630,6 +650,125 @@
                        status = "disabled";
                };
 
+               qupv3_id_0: geniqup@4ac0000 {
+                       compatible = "qcom,geni-se-qup";
+                       reg = <0x0 0x04ac0000 0x0 0x2000>;
+                       clock-names = "m-ahb", "s-ahb";
+                       clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+                                <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+                       iommus = <&apps_smmu 0x3 0x0>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+                       status = "disabled";
+
+                       i2c0: i2c@4a80000 {
+                               compatible = "qcom,geni-i2c";
+                               reg = <0x0 0x04a80000 0x0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+                               interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&qup_i2c0_default>;
+                               dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+                                      <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       spi0: spi@4a80000 {
+                               compatible = "qcom,geni-spi";
+                               reg = <0x0 0x04a80000 0x0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+                               interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&qup_spi0_default>;
+                               power-domains = <&rpmpd SM6375_VDDCX>;
+                               operating-points-v2 = <&qup_opp_table>;
+                               dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+                                      <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       i2c1: i2c@4a84000 {
+                               compatible = "qcom,geni-i2c";
+                               reg = <0x0 0x04a84000 0x0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+                               interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&qup_i2c1_default>;
+                               dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+                                      <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       spi1: spi@4a84000 {
+                               compatible = "qcom,geni-spi";
+                               reg = <0x0 0x04a84000 0x0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+                               interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+                               power-domains = <&rpmpd SM6375_VDDCX>;
+                               operating-points-v2 = <&qup_opp_table>;
+                               dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
+                                      <&gpi_dma0 1 1 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       i2c2: i2c@4a88000 {
+                               compatible = "qcom,geni-i2c";
+                               reg = <0x0 0x04a88000 0x0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+                               interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&qup_i2c2_default>;
+                               dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+                                      <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       spi2: spi@4a88000 {
+                               compatible = "qcom,geni-spi";
+                               reg = <0x0 0x04a88000 0x0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+                               interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+                               power-domains = <&rpmpd SM6375_VDDCX>;
+                               operating-points-v2 = <&qup_opp_table>;
+                               dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+                                      <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       /*
+                        * As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream.
+                        * There is a comment in the included DTSI of another SoC saying that they
+                        * are not "bolled out" (probably meaning not routed to solder balls)
+                        * TLMM driver however, suggests there are as many as 15 QUPs in total!
+                        * Most of which don't even have pin configurations for.. Sad stuff!
+                        */
+               };
+
                gpi_dma1: dma-controller@4c00000 {
                        compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma";
                        reg = <0 0x04c00000 0 0x60000>;
@@ -650,6 +789,173 @@
                        status = "disabled";
                };
 
+               qupv3_id_1: geniqup@4cc0000 {
+                       compatible = "qcom,geni-se-qup";
+                       reg = <0x0 0x04cc0000 0x0 0x2000>;
+                       clock-names = "m-ahb", "s-ahb";
+                       clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+                                <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+                       iommus = <&apps_smmu 0xc3 0x0>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+                       status = "disabled";
+
+                       i2c6: i2c@4c80000 {
+                               compatible = "qcom,geni-i2c";
+                               reg = <0x0 0x04c80000 0x0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+                               interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       spi6: spi@4c80000 {
+                               compatible = "qcom,geni-spi";
+                               reg = <0x0 0x04c80000 0x0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+                               interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
+                               power-domains = <&rpmpd SM6375_VDDCX>;
+                               operating-points-v2 = <&qup_opp_table>;
+                               dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       i2c7: i2c@4c84000 {
+                               compatible = "qcom,geni-i2c";
+                               reg = <0x0 0x04c84000 0x0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+                               interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       spi7: spi@4c84000 {
+                               compatible = "qcom,geni-spi";
+                               reg = <0x0 0x04c84000 0x0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+                               interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+                               power-domains = <&rpmpd SM6375_VDDCX>;
+                               operating-points-v2 = <&qup_opp_table>;
+                               dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       i2c8: i2c@4c88000 {
+                               compatible = "qcom,geni-i2c";
+                               reg = <0x0 0x04c88000 0x0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+                               interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&qup_i2c8_default>;
+                               dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       spi8: spi@4c88000 {
+                               compatible = "qcom,geni-spi";
+                               reg = <0x0 0x04c88000 0x0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+                               interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+                               power-domains = <&rpmpd SM6375_VDDCX>;
+                               operating-points-v2 = <&qup_opp_table>;
+                               dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       i2c9: i2c@4c8c000 {
+                               compatible = "qcom,geni-i2c";
+                               reg = <0x0 0x04c8c000 0x0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+                               interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       spi9: spi@4c8c000 {
+                               compatible = "qcom,geni-spi";
+                               reg = <0x0 0x04c8c000 0x0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+                               interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>;
+                               power-domains = <&rpmpd SM6375_VDDCX>;
+                               operating-points-v2 = <&qup_opp_table>;
+                               dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       i2c10: i2c@4c90000 {
+                               compatible = "qcom,geni-i2c";
+                               reg = <0x0 0x04c90000 0x0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+                               interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&qup_i2c10_default>;
+                               dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       spi10: spi@4c90000 {
+                               compatible = "qcom,geni-spi";
+                               reg = <0x0 0x04c90000 0x0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+                               interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>;
+                               power-domains = <&rpmpd SM6375_VDDCX>;
+                               operating-points-v2 = <&qup_opp_table>;
+                               dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+               };
+
                usb_1: usb@4ef8800 {
                        compatible = "qcom,sm6375-dwc3", "qcom,dwc3";
                        reg = <0 0x04ef8800 0 0x400>;