Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/kernel...

Pull RISC-V updates from Palmer Dabbelt:
 "This contains an assortment of RISC-V related patches that I'd like to
  target for the 5.2 merge window. Most of the patches are cleanups, but
  there are a handful of user-visible changes:

   - The nosmp and nr_cpus command-line arguments are now supported,
     which work like normal.

   - The SBI console no longer installs itself as a preferred console,
     we rely on standard mechanisms (/chosen, command-line, hueristics)
     instead.

   - sfence_remove_sfence_vma{,_asid} now pass their arguments along to
     the SBI call.

   - Modules now support BUG().

   - A missing sfence.vma during boot has been added. This bug only
     manifests during boot.

   - The arch/riscv support for SiFive's L2 cache controller has been
     merged, which should un-block the EDAC framework work.

  I've only tested this on QEMU again, as I didn't have time to get
  things running on the Unleashed. The latest master from this morning
  merges in cleanly and passes the tests as well"

* tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux: (31 commits)
  riscv: fix locking violation in page fault handler
  RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs
  RISC-V: Add DT documentation for SiFive L2 Cache Controller
  RISC-V: Avoid using invalid intermediate translations
  riscv: Support BUG() in kernel module
  riscv: Add the support for c.ebreak check in is_valid_bugaddr()
  riscv: support trap-based WARN()
  riscv: fix sbi_remote_sfence_vma{,_asid}.
  riscv: move switch_mm to its own file
  riscv: move flush_icache_{all,mm} to cacheflush.c
  tty: Don't force RISCV SBI console as preferred console
  RISC-V: Access CSRs using CSR numbers
  RISC-V: Add interrupt related SCAUSE defines in asm/csr.h
  RISC-V: Use tabs to align macro values in asm/csr.h
  RISC-V: Fix minor checkpatch issues.
  RISC-V: Support nr_cpus command line option.
  RISC-V: Implement nosmp commandline option.
  RISC-V: Add RISC-V specific arch_match_cpu_phys_id
  riscv: vdso: drop unnecessary cc-ldoption
  riscv: call pm_power_off from machine_halt / machine_power_off
  ...

diff --combined arch/riscv/Kconfig
index e66745d,a65b2a4..ee32c66
--- 1/arch/riscv/Kconfig
--- 2/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@@ -27,7 -27,7 +27,7 @@@ config RISC
        select GENERIC_STRNCPY_FROM_USER
        select GENERIC_STRNLEN_USER
        select GENERIC_SMP_IDLE_THREAD
-       select GENERIC_ATOMIC64 if !64BIT || !RISCV_ISA_A
+       select GENERIC_ATOMIC64 if !64BIT
        select HAVE_ARCH_AUDITSYSCALL
        select HAVE_MEMBLOCK_NODE_MAP
        select HAVE_DMA_CONTIGUOUS
@@@ -35,7 -35,6 +35,6 @@@
        select HAVE_PERF_EVENTS
        select HAVE_SYSCALL_TRACEPOINTS
        select IRQ_DOMAIN
-       select RISCV_ISA_A if SMP
        select SPARSE_IRQ
        select SYSCTL_EXCEPTION_TRACE
        select HAVE_ARCH_TRACEHOOK
@@@ -48,7 -47,6 +47,7 @@@
        select RISCV_TIMER
        select GENERIC_IRQ_MULTI_HANDLER
        select ARCH_HAS_PTE_SPECIAL
 +      select ARCH_HAS_MMIOWB
        select HAVE_EBPF_JIT if 64BIT
  
  config MMU
@@@ -70,6 -68,9 +69,6 @@@ config STACKTRACE_SUPPOR
  config TRACE_IRQFLAGS_SUPPORT
        def_bool y
  
 -config RWSEM_GENERIC_SPINLOCK
 -      def_bool y
 -
  config GENERIC_BUG
        def_bool y
        depends on BUG
@@@ -195,9 -196,6 +194,6 @@@ config RISCV_ISA_
  
           If you don't know what to do here, say Y.
  
- config RISCV_ISA_A
-       def_bool y
- 
  menu "supported PMU type"
        depends on PERF_EVENTS
  

diff --combined arch/riscv/kernel/stacktrace.c
index 4d40327,a4386a0..e80a5e8
--- 1/arch/riscv/kernel/stacktrace.c
--- 2/arch/riscv/kernel/stacktrace.c
+++ b/arch/riscv/kernel/stacktrace.c
@@@ -33,9 -33,9 +33,9 @@@ static void notrace walk_stackframe(str
        unsigned long fp, sp, pc;
  
        if (regs) {
-               fp = GET_FP(regs);
-               sp = GET_USP(regs);
-               pc = GET_IP(regs);
+               fp = frame_pointer(regs);
+               sp = user_stack_pointer(regs);
+               pc = instruction_pointer(regs);
        } else if (task == NULL || task == current) {
                const register unsigned long current_sp __asm__ ("sp");
                fp = (unsigned long)__builtin_frame_address(0);
@@@ -64,12 -64,8 +64,8 @@@
                frame = (struct stackframe *)fp - 1;
                sp = fp;
                fp = frame->fp;
- #ifdef HAVE_FUNCTION_GRAPH_RET_ADDR_PTR
                pc = ftrace_graph_ret_addr(current, NULL, frame->ra,
                                           (unsigned long *)(fp - 8));
- #else
-               pc = frame->ra - 0x4;
- #endif
        }
  }
  
@@@ -82,8 -78,8 +78,8 @@@ static void notrace walk_stackframe(str
        unsigned long *ksp;
  
        if (regs) {
-               sp = GET_USP(regs);
-               pc = GET_IP(regs);
+               sp = user_stack_pointer(regs);
+               pc = instruction_pointer(regs);
        } else if (task == NULL || task == current) {
                const register unsigned long current_sp __asm__ ("sp");
                sp = current_sp;
@@@ -169,6 -165,8 +165,6 @@@ static bool save_trace(unsigned long pc
  void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
  {
        walk_stackframe(tsk, NULL, save_trace, trace);
 -      if (trace->nr_entries < trace->max_entries)
 -              trace->entries[trace->nr_entries++] = ULONG_MAX;
  }
  EXPORT_SYMBOL_GPL(save_stack_trace_tsk);