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ARM: DTS: exynos5420: add GSCL block parent clock management to pm domain
author
Marek Szyprowski
<m.szyprowski@samsung.com>
Tue, 1 Sep 2015 09:23:09 +0000
(11:23 +0200)
committer
Seung-Woo Kim
<sw0312.kim@samsung.com>
Wed, 14 Dec 2016 04:50:35 +0000
(13:50 +0900)
Add support for restoring GSCALLER parent clocks configuration when GSCL
power domain is turned on.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
arch/arm/boot/dts/exynos5420.dtsi
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diff --git
a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index
1711c9b
..
907923e
100644
(file)
--- a/
arch/arm/boot/dts/exynos5420.dtsi
+++ b/
arch/arm/boot/dts/exynos5420.dtsi
@@
-299,8
+299,10
@@
compatible = "samsung,exynos4210-pd";
reg = <0x10044000 0x20>;
#power-domain-cells = <0>;
- clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>, <&clock CLK_FIMC_3AA>;
- clock-names = "asb0", "asb1", "asb2";
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK300_GSCL>,
+ <&clock CLK_MOUT_USER_ACLK300_GSCL>, <&clock CLK_GSCL0>,
+ <&clock CLK_GSCL1>, <&clock CLK_FIMC_3AA>;
+ clock-names = "oscclk", "pclk0", "clk0", "asb0", "asb1", "asb2";
};
isp_pd: power-domain@10044020 {