mmc: s5p_sdhci: add the set_mmc_clk for cmu control
authorJaehoon Chung <jh80.chung@samsung.com>
Thu, 30 Aug 2012 16:24:11 +0000 (16:24 +0000)
committerAndy Fleming <afleming@freescale.com>
Wed, 5 Sep 2012 22:33:26 +0000 (17:33 -0500)
Samsung SoC use the cmu control to set clock.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
drivers/mmc/s5p_sdhci.c
drivers/mmc/sdhci.c
include/configs/trats.h
include/sdhci.h

index 9378e36..b978236 100644 (file)
@@ -21,6 +21,7 @@
 #include <malloc.h>
 #include <sdhci.h>
 #include <asm/arch/mmc.h>
+#include <asm/arch/clk.h>
 
 static char *S5P_NAME = "SAMSUNG SDHCI";
 static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
@@ -87,6 +88,8 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width)
        host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 
        host->set_control_reg = &s5p_sdhci_set_control_reg;
+       host->set_clock = set_mmc_clk;
+       host->index = index;
 
        host->host_caps = MMC_MODE_HC;
 
index 3bb0ad0..2e3c408 100644 (file)
@@ -279,6 +279,9 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
        }
        div >>= 1;
 
+       if (host->set_clock)
+               host->set_clock(host->index, div);
+
        clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
        clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
                << SDHCI_DIVIDER_HI_SHIFT;
index f8da9c0..794b6fb 100644 (file)
@@ -78,6 +78,7 @@
 #define CONFIG_MMC
 #define CONFIG_S5P_SDHCI
 #define CONFIG_SDHCI
+#define CONFIG_MMC_SDMA
 
 /* PWM */
 #define CONFIG_PWM
index d41287f..c0345ed 100644 (file)
@@ -253,8 +253,10 @@ struct sdhci_host {
        unsigned int clock;
        struct mmc *mmc;
        const struct sdhci_ops *ops;
+       int index;
 
        void (*set_control_reg)(struct sdhci_host *host);
+       void (*set_clock)(int dev_index, unsigned int div);
        uint    voltages;
 };