ASoC: SOF: Intel: hda: add SSP info to the chip info struct
authorZhu Yingjiang <yingjiang.zhu@linux.intel.com>
Tue, 30 Apr 2019 23:09:21 +0000 (18:09 -0500)
committerMark Brown <broonie@kernel.org>
Fri, 3 May 2019 05:57:39 +0000 (14:57 +0900)
add SSP info of APL and CNL, to the sof_intel_dsp_desc
structure. The max SSP count the platform support and
the SSP base address.

Signed-off-by: Zhu Yingjiang <yingjiang.zhu@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/sof/intel/apl.c
sound/soc/sof/intel/cnl.c
sound/soc/sof/intel/hda.h
sound/soc/sof/intel/shim.h

index 8c62826..026dde8 100644 (file)
@@ -105,5 +105,7 @@ const struct sof_intel_dsp_desc apl_chip_info = {
        .ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
        .ipc_ctl = HDA_DSP_REG_HIPCCTL,
        .rom_init_timeout       = 150,
+       .ssp_count = APL_SSP_COUNT,
+       .ssp_base_offset = APL_SSP_BASE_OFFSET,
 };
 EXPORT_SYMBOL(apl_chip_info);
index 36ae9b8..3afd96d 100644 (file)
@@ -246,5 +246,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
        .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
        .ipc_ctl = CNL_DSP_REG_HIPCCTL,
        .rom_init_timeout       = 300,
+       .ssp_count = CNL_SSP_COUNT,
+       .ssp_base_offset = CNL_SSP_BASE_OFFSET,
 };
 EXPORT_SYMBOL(cnl_chip_info);
index c4550f2..b2cf6fa 100644 (file)
 /* Host Device Memory Size of a Single SSP */
 #define SSP_DEV_MEM_SIZE       0x1000
 
+/* SSP Count of the Platform */
+#define APL_SSP_COUNT          6
+#define CNL_SSP_COUNT          3
+
 #define HDA_IDISP_CODEC(x) ((x) & BIT(2))
 
 struct sof_intel_dsp_bdl {
index 11fd77c..f7a3f62 100644 (file)
@@ -162,6 +162,8 @@ struct sof_intel_dsp_desc {
        int ipc_ack_mask;
        int ipc_ctl;
        int rom_init_timeout;
+       int ssp_count;                  /* ssp count of the platform */
+       int ssp_base_offset;            /* base address of the SSPs */
 };
 
 extern const struct snd_sof_dsp_ops sof_tng_ops;