phy: mediatek: hdmi: mt2701: use GENMASK and BIT to generate mask and bits

Use GENMASK() and BIT() macros to generate mask and bits

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220920090038.15133-7-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
index b74c65a..ce36f37 100644 (file)
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
@@ -8,62 +8,62 @@
 
 #define HDMI_CON0      0x00
 #define RG_HDMITX_DRV_IBIAS            0
-#define RG_HDMITX_DRV_IBIAS_MASK       (0x3f << 0)
+#define RG_HDMITX_DRV_IBIAS_MASK       GENMASK(5, 0)
 #define RG_HDMITX_EN_SER               12
-#define RG_HDMITX_EN_SER_MASK          (0x0f << 12)
+#define RG_HDMITX_EN_SER_MASK          GENMASK(15, 12)
 #define RG_HDMITX_EN_SLDO              16
-#define RG_HDMITX_EN_SLDO_MASK         (0x0f << 16)
+#define RG_HDMITX_EN_SLDO_MASK         GENMASK(19, 16)
 #define RG_HDMITX_EN_PRED              20
-#define RG_HDMITX_EN_PRED_MASK         (0x0f << 20)
+#define RG_HDMITX_EN_PRED_MASK         GENMASK(23, 20)
 #define RG_HDMITX_EN_IMP               24
-#define RG_HDMITX_EN_IMP_MASK          (0x0f << 24)
+#define RG_HDMITX_EN_IMP_MASK          GENMASK(27, 24)
 #define RG_HDMITX_EN_DRV               28
-#define RG_HDMITX_EN_DRV_MASK          (0x0f << 28)
+#define RG_HDMITX_EN_DRV_MASK          GENMASK(31, 28)
 
 #define HDMI_CON1      0x04
 #define RG_HDMITX_PRED_IBIAS           18
-#define RG_HDMITX_PRED_IBIAS_MASK      (0x0f << 18)
-#define RG_HDMITX_PRED_IMP             (0x01 << 22)
+#define RG_HDMITX_PRED_IBIAS_MASK      GENMASK(21, 18)
+#define RG_HDMITX_PRED_IMP             BIT(22)
 #define RG_HDMITX_DRV_IMP              26
-#define RG_HDMITX_DRV_IMP_MASK         (0x3f << 26)
+#define RG_HDMITX_DRV_IMP_MASK         GENMASK(31, 26)
 
 #define HDMI_CON2      0x08
-#define RG_HDMITX_EN_TX_CKLDO          (0x01 << 0)
-#define RG_HDMITX_EN_TX_POSDIV         (0x01 << 1)
+#define RG_HDMITX_EN_TX_CKLDO          BIT(0)
+#define RG_HDMITX_EN_TX_POSDIV         BIT(1)
 #define RG_HDMITX_TX_POSDIV            3
-#define RG_HDMITX_TX_POSDIV_MASK       (0x03 << 3)
-#define RG_HDMITX_EN_MBIAS             (0x01 << 6)
-#define RG_HDMITX_MBIAS_LPF_EN         (0x01 << 7)
+#define RG_HDMITX_TX_POSDIV_MASK       GENMASK(4, 3)
+#define RG_HDMITX_EN_MBIAS             BIT(6)
+#define RG_HDMITX_MBIAS_LPF_EN         BIT(7)
 
 #define HDMI_CON4      0x10
-#define RG_HDMITX_RESERVE_MASK         (0xffffffff << 0)
+#define RG_HDMITX_RESERVE_MASK         GENMASK(31, 0)
 
 #define HDMI_CON6      0x18
 #define RG_HTPLL_BR                    0
-#define RG_HTPLL_BR_MASK               (0x03 << 0)
+#define RG_HTPLL_BR_MASK               GENMASK(1, 0)
 #define RG_HTPLL_BC                    2
-#define RG_HTPLL_BC_MASK               (0x03 << 2)
+#define RG_HTPLL_BC_MASK               GENMASK(3, 2)
 #define RG_HTPLL_BP                    4
-#define RG_HTPLL_BP_MASK               (0x0f << 4)
+#define RG_HTPLL_BP_MASK               GENMASK(7, 4)
 #define RG_HTPLL_IR                    8
-#define RG_HTPLL_IR_MASK               (0x0f << 8)
+#define RG_HTPLL_IR_MASK               GENMASK(11, 8)
 #define RG_HTPLL_IC                    12
-#define RG_HTPLL_IC_MASK               (0x0f << 12)
+#define RG_HTPLL_IC_MASK               GENMASK(15, 12)
 #define RG_HTPLL_POSDIV                        16
-#define RG_HTPLL_POSDIV_MASK           (0x03 << 16)
+#define RG_HTPLL_POSDIV_MASK           GENMASK(17, 16)
 #define RG_HTPLL_PREDIV                        18
-#define RG_HTPLL_PREDIV_MASK           (0x03 << 18)
+#define RG_HTPLL_PREDIV_MASK           GENMASK(19, 18)
 #define RG_HTPLL_FBKSEL                        20
-#define RG_HTPLL_FBKSEL_MASK           (0x03 << 20)
-#define RG_HTPLL_RLH_EN                        (0x01 << 22)
+#define RG_HTPLL_FBKSEL_MASK           GENMASK(21, 20)
+#define RG_HTPLL_RLH_EN                        BIT(22)
 #define RG_HTPLL_FBKDIV                        24
-#define RG_HTPLL_FBKDIV_MASK           (0x7f << 24)
-#define RG_HTPLL_EN                    (0x01 << 31)
+#define RG_HTPLL_FBKDIV_MASK           GENMASK(30, 24)
+#define RG_HTPLL_EN                    BIT(31)
 
 #define HDMI_CON7      0x1c
-#define RG_HTPLL_AUTOK_EN              (0x01 << 23)
+#define RG_HTPLL_AUTOK_EN              BIT(23)
 #define RG_HTPLL_DIVEN                 28
-#define RG_HTPLL_DIVEN_MASK            (0x07 << 28)
+#define RG_HTPLL_DIVEN_MASK            GENMASK(30, 28)
 
 static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
 {