+2016-01-06 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * elf32-arc.c (reloc_type_to_name): Change ARC_RELOC_HOWTO to
+ place 'R_' before the reloc name returned.
+ (elf_arc_howto_table): Change ARC_RELOC_HOWTO to place 'R_' before
+ the relocation string.
+
2016-01-04 Maciej W. Rozycki <macro@imgtec.com>
* elfxx-mips.c (mips_elf_merge_obj_abiflags): New function,
#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
case VALUE: \
- return #TYPE; \
+ return "R_" #TYPE; \
break;
static ATTRIBUTE_UNUSED const char *
#undef ARC_RELOC_HOWTO
#define ARC_RELOC_HOWTO(TYPE, VALUE, RSIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
- [TYPE] = HOWTO (R_##TYPE, 0, RSIZE, BITSIZE, FALSE, 0, complain_overflow_##OVERFLOW, arc_elf_reloc, #TYPE, FALSE, 0, 0, FALSE),
+ [TYPE] = HOWTO (R_##TYPE, 0, RSIZE, BITSIZE, FALSE, 0, complain_overflow_##OVERFLOW, arc_elf_reloc, "R_" #TYPE, FALSE, 0, 0, FALSE),
static struct reloc_howto_struct elf_arc_howto_table[] =
{
+2016-01-06 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * testsuite/gas/arc/adc.d: Add 'R_' prefix to relocation names.
+ * testsuite/gas/arc/add.d: Likewise.
+ * testsuite/gas/arc/and.d: Likewise.
+ * testsuite/gas/arc/asl.d: Likewise.
+ * testsuite/gas/arc/asr.d: Likewise.
+ * testsuite/gas/arc/bic.d: Likewise.
+ * testsuite/gas/arc/extb.d: Likewise.
+ * testsuite/gas/arc/extw.d: Likewise.
+ * testsuite/gas/arc/j.d: Likewise.
+ * testsuite/gas/arc/jl.d: Likewise.
+ * testsuite/gas/arc/ld2.d: Likewise.
+ * testsuite/gas/arc/lsr.d: Likewise.
+ * testsuite/gas/arc/mov.d: Likewise.
+ * testsuite/gas/arc/or.d: Likewise.
+ * testsuite/gas/arc/pcl-relocs.d: Likewise.
+ * testsuite/gas/arc/pcrel-relocs.d: Likewise.
+ * testsuite/gas/arc/pic-relocs.d: Likewise.
+ * testsuite/gas/arc/plt-relocs.d: Likewise.
+ * testsuite/gas/arc/rlc.d: Likewise.
+ * testsuite/gas/arc/ror.d: Likewise.
+ * testsuite/gas/arc/rrc.d: Likewise.
+ * testsuite/gas/arc/sbc.d: Likewise.
+ * testsuite/gas/arc/sda-relocs.d: Likewise.
+ * testsuite/gas/arc/sda-relocs2.d: Likewise.
+ * testsuite/gas/arc/sexb.d: Likewise.
+ * testsuite/gas/arc/sexw.d: Likewise.
+ * testsuite/gas/arc/st.d: Likewise.
+ * testsuite/gas/arc/sub.d: Likewise.
+ * testsuite/gas/arc/tls-relocs.d: Likewise.
+ * testsuite/gas/arc/xor.d: Likewise.
+
2016-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
0x[0-9a-f]+ 2601 7080 ffff feff adc r0,0xfffffeff,r2
0x[0-9a-f]+ 2601 7f80 0000 0100 adc r0,0x100,0x100
0x[0-9a-f]+ 2101 0f80 0000 0000 adc r0,r1,0
- 68: ARC_32_ME foo
+ 68: R_ARC_32_ME foo
0x[0-9a-f]+ 20c1 0080 adc r0,r0,r2
0x[0-9a-f]+ 23c1 0140 adc r3,r3,r5
0x[0-9a-f]+ 26c1 0201 adc.eq r6,r6,r8
0x[0-9a-f]+ 2600 7080 ffff feff add r0,0xfffffeff,r2
0x[0-9a-f]+ 2600 7f80 0000 0100 add r0,0x100,0x100
0x[0-9a-f]+ 2100 0f80 0000 0000 add r0,r1,0
- 68: ARC_32_ME foo
+ 68: R_ARC_32_ME foo
0x[0-9a-f]+ 20c0 0080 add r0,r0,r2
0x[0-9a-f]+ 23c0 0140 add r3,r3,r5
0x[0-9a-f]+ 26c0 0201 add.eq r6,r6,r8
0x[0-9a-f]+ 2604 7080 ffff feff and r0,0xfffffeff,r2
0x[0-9a-f]+ 2604 7f80 0000 0100 and r0,0x100,0x100
0x[0-9a-f]+ 2104 0f80 0000 0000 and r0,r1,0
- 68: ARC_32_ME foo
+ 68: R_ARC_32_ME foo
0x[0-9a-f]+ 20c4 0080 and r0,r0,r2
0x[0-9a-f]+ 23c4 0140 and r3,r3,r5
0x[0-9a-f]+ 26c4 0201 and.eq r6,r6,r8
0x[0-9a-f]+ 2e00 7080 ffff feff asl r0,0xfffffeff,r2
0x[0-9a-f]+ 2e00 7f80 0000 0100 asl r0,0x100,0x100
0x[0-9a-f]+ 2900 0f80 0000 0000 asl r0,r1,0
- 68: ARC_32_ME foo
+ 68: R_ARC_32_ME foo
0x[0-9a-f]+ 28c0 0080 asl r0,r0,r2
0x[0-9a-f]+ 2bc0 0140 asl r3,r3,r5
0x[0-9a-f]+ 2ec0 0201 asl.eq r6,r6,r8
0x[0-9a-f]+ 2e02 7080 ffff feff asr r0,0xfffffeff,r2
0x[0-9a-f]+ 2e02 7f80 0000 0100 asr r0,0x100,0x100
0x[0-9a-f]+ 2902 0f80 0000 0000 asr r0,r1,0
- 68: ARC_32_ME foo
+ 68: R_ARC_32_ME foo
0x[0-9a-f]+ 28c2 0080 asr r0,r0,r2
0x[0-9a-f]+ 2bc2 0140 asr r3,r3,r5
0x[0-9a-f]+ 2ec2 0201 asr.eq r6,r6,r8
0x[0-9a-f]+ 2606 7080 ffff feff bic r0,0xfffffeff,r2
0x[0-9a-f]+ 2606 7f80 0000 0100 bic r0,0x100,0x100
0x[0-9a-f]+ 2106 0f80 0000 0000 bic r0,r1,0
- 68: ARC_32_ME foo
+ 68: R_ARC_32_ME foo
0x[0-9a-f]+ 20c6 0080 bic r0,r0,r2
0x[0-9a-f]+ 23c6 0140 bic r3,r3,r5
0x[0-9a-f]+ 26c6 0201 bic.eq r6,r6,r8
0x[0-9a-f]+ 212f 1f87 ffff feff extb r9,0xfffffeff
0x[0-9a-f]+ 232f 1f87 4242 4242 extb r11,0x42424242
0x[0-9a-f]+ 202f 0f87 0000 0000 extb r0,0
- 44: ARC_32_ME foo
+ 44: R_ARC_32_ME foo
0x[0-9a-f]+ 202f 8047 extb.f r0,r1
0x[0-9a-f]+ 226f 8047 extb.f r2,0x1
0x[0-9a-f]+ 262f f107 extb.f 0,r4
0x00000030 212f 1f88 ffff feff ext[hw]+ r9,0xfffffeff
0x00000038 232f 1f88 4242 4242 ext[hw]+ r11,0x42424242
0x00000040 202f 0f88 0000 0000 ext[hw]+ r0,0
- 44: ARC_32_ME foo
+ 44: R_ARC_32_ME foo
0x00000048 202f 8048 ext[hw]+.f r0,r1
0x0000004c 226f 8048 ext[hw]+.f r2,0x1
0x00000050 262f f108 ext[hw]+.f 0,r4
[0-9a-f]+ <text_label>:
0: 2020 0f80 0000 0000 j 0
- 4: ARC_32_ME text_label
+ 4: R_ARC_32_ME text_label
8: 20e0 0f80 0000 0000 j 0
- c: ARC_32_ME text_label
+ c: R_ARC_32_ME text_label
10: 20e0 0f80 0000 0000 j 0
- 14: ARC_32_ME text_label
+ 14: R_ARC_32_ME text_label
18: 20e0 0f81 0000 0000 jeq 0
- 1c: ARC_32_ME text_label
+ 1c: R_ARC_32_ME text_label
20: 20e0 0f81 0000 0000 jeq 0
- 24: ARC_32_ME text_label
+ 24: R_ARC_32_ME text_label
28: 20e0 0f82 0000 0000 jne 0
- 2c: ARC_32_ME text_label
+ 2c: R_ARC_32_ME text_label
30: 20e0 0f82 0000 0000 jne 0
- 34: ARC_32_ME text_label
+ 34: R_ARC_32_ME text_label
38: 20e0 0f83 0000 0000 jp 0
- 3c: ARC_32_ME text_label
+ 3c: R_ARC_32_ME text_label
40: 20e0 0f83 0000 0000 jp 0
- 44: ARC_32_ME text_label
+ 44: R_ARC_32_ME text_label
48: 20e0 0f84 0000 0000 jn 0
- 4c: ARC_32_ME text_label
+ 4c: R_ARC_32_ME text_label
50: 20e0 0f84 0000 0000 jn 0
- 54: ARC_32_ME text_label
+ 54: R_ARC_32_ME text_label
58: 20e0 0f85 0000 0000 jc 0
- 5c: ARC_32_ME text_label
+ 5c: R_ARC_32_ME text_label
60: 20e0 0f85 0000 0000 jc 0
- 64: ARC_32_ME text_label
+ 64: R_ARC_32_ME text_label
68: 20e0 0f85 0000 0000 jc 0
- 6c: ARC_32_ME text_label
+ 6c: R_ARC_32_ME text_label
70: 20e0 0f86 0000 0000 jnc 0
- 74: ARC_32_ME text_label
+ 74: R_ARC_32_ME text_label
78: 20e0 0f86 0000 0000 jnc 0
- 7c: ARC_32_ME text_label
+ 7c: R_ARC_32_ME text_label
80: 20e0 0f86 0000 0000 jnc 0
- 84: ARC_32_ME text_label
+ 84: R_ARC_32_ME text_label
88: 20e0 0f87 0000 0000 jv 0
- 8c: ARC_32_ME text_label
+ 8c: R_ARC_32_ME text_label
90: 20e0 0f87 0000 0000 jv 0
- 94: ARC_32_ME text_label
+ 94: R_ARC_32_ME text_label
98: 20e0 0f88 0000 0000 jnv 0
- 9c: ARC_32_ME text_label
+ 9c: R_ARC_32_ME text_label
a0: 20e0 0f88 0000 0000 jnv 0
- a4: ARC_32_ME text_label
+ a4: R_ARC_32_ME text_label
a8: 20e0 0f89 0000 0000 jgt 0
- ac: ARC_32_ME text_label
+ ac: R_ARC_32_ME text_label
b0: 20e0 0f8a 0000 0000 jge 0
- b4: ARC_32_ME text_label
+ b4: R_ARC_32_ME text_label
b8: 20e0 0f8b 0000 0000 jlt 0
- bc: ARC_32_ME text_label
+ bc: R_ARC_32_ME text_label
c0: 20e0 0f8c 0000 0000 jle 0
- c4: ARC_32_ME text_label
+ c4: R_ARC_32_ME text_label
c8: 20e0 0f8d 0000 0000 jhi 0
- cc: ARC_32_ME text_label
+ cc: R_ARC_32_ME text_label
d0: 20e0 0f8e 0000 0000 jls 0
- d4: ARC_32_ME text_label
+ d4: R_ARC_32_ME text_label
d8: 20e0 0f8f 0000 0000 jpnz 0
- dc: ARC_32_ME text_label
+ dc: R_ARC_32_ME text_label
e0: 2020 0f80 0000 0000 j 0
- e4: ARC_32_ME external_text_label
+ e4: R_ARC_32_ME external_text_label
e8: 20a0 0000 j 0
[0-9a-f]+ <text_label>:
0: 2022 0f80 0000 0000 jl 0
- 4: ARC_32_ME text_label
+ 4: R_ARC_32_ME text_label
8: 20e3 0042 jlne.d \[r1\]
c: 78e0 nop_s
e: 20e2 0f80 0000 0000 jl 0
- 12: ARC_32_ME text_label
+ 12: R_ARC_32_ME text_label
0: 1100 0000 ld r0,\[r1\]
4: 1601 0005 ld r5,\[r6,1\]
8: 1600 7013 0000 0000 ld r19,\[0\]
- c: ARC_32_ME foo
+ c: R_ARC_32_ME foo
10: 120a 0204 ld.aw r4,\[r2,10\]
14: 1600 7001 0000 0384 ld r1,\[0x384\]
1c: 130f 0082 ldb r2,\[r3,15\]
0x[0-9a-f]+ 2e01 7080 ffff feff lsr r0,0xfffffeff,r2
0x[0-9a-f]+ 2e01 7f80 0000 0100 lsr r0,0x100,0x100
0x[0-9a-f]+ 2901 0f80 0000 0000 lsr r0,r1,0
- 68: ARC_32_ME foo
+ 68: R_ARC_32_ME foo
0x[0-9a-f]+ 28c1 0080 lsr r0,r0,r2
0x[0-9a-f]+ 2bc1 0140 lsr r3,r3,r5
0x[0-9a-f]+ 2ec1 0201 lsr.eq r6,r6,r8
0x[0-9a-f]+ 230a 1f80 4242 4242 mov r11,0x42424242
0x[0-9a-f]+ 260a 7f80 1234 5678 mov 0,0x12345678
0x[0-9a-f]+ 200a 0f80 0000 0000 mov r0,0
- 34: ARC_32_ME foo
+ 34: R_ARC_32_ME foo
0x[0-9a-f]+ 20ca 0040 mov r0,r1
0x[0-9a-f]+ 23ca 0100 mov r3,r4
0x[0-9a-f]+ 26ca 01c1 mov.eq r6,r7
0x[0-9a-f]+ 2605 7080 ffff feff or r0,0xfffffeff,r2
0x[0-9a-f]+ 2605 7f80 0000 0100 or r0,0x100,0x100
0x[0-9a-f]+ 2105 0f80 0000 0000 or r0,r1,0
- 68: ARC_32_ME foo
+ 68: R_ARC_32_ME foo
0x[0-9a-f]+ 20c5 0080 or r0,r0,r2
0x[0-9a-f]+ 23c5 0140 or r3,r3,r5
0x[0-9a-f]+ 26c5 0201 or.eq r6,r6,r8
Disassembly of section .text:
0x[0-9a-f]+ 2700 7f80 0000 0000 add r0,pcl,0
- 4: ARC_PC32 var
+ 4: R_ARC_PC32 var
0x[0-9a-f]+ 2736 7f86 0000 0000 ldd r6r7,\[pcl,0\]
- c: ARC_PC32 var
+ c: R_ARC_PC32 var
0x[0-9a-f]+ 2730 7f83 0000 0000 ld r3,\[pcl,0\]
- 14: ARC_PC32 var
+ 14: R_ARC_PC32 var
Disassembly of section .text:
0x[0-9a-f]+ 0000 0002 bne 0
- 0: ARC_S21H_PCREL printf
+ 0: R_ARC_S21H_PCREL printf
0x[0-9a-f]+ 0800 0002 blne 0x00000000
- 4: ARC_S21W_PCREL printf
+ 4: R_ARC_S21W_PCREL printf
0x[0-9a-f]+ 0001 0000 b 0x00000000
- 8: ARC_S25H_PCREL printf
+ 8: R_ARC_S25H_PCREL printf
0x[0-9a-f]+ 0802 0000 bl 0x00000000
- c: ARC_S25W_PCREL printf
+ c: R_ARC_S25W_PCREL printf
0x[0-9a-f]+ f800 bl_s 0x00000000
- 10: ARC_S13_PCREL printf
+ 10: R_ARC_S13_PCREL printf
Disassembly of section .text:
0x[0-9a-f]+ 2730 7f82 0000 0000 ld r2,\[pcl,0\]
- 4: ARC_GOTPC32 var
+ 4: R_ARC_GOTPC32 var
0x[0-9a-f]+ 2700 7f9a 0000 0000 add gp,pcl,0
- c: ARC_GOTPC32 var
+ c: R_ARC_GOTPC32 var
0x[0-9a-f]+ 2200 3f82 0000 0000 add r2,gp,0
- 14: ARC_GOTOFF var
+ 14: R_ARC_GOTOFF var
Disassembly of section .text:
0x[0-9a-f]+ 0000 0002 bne 0
- 0: ARC_S21H_PCREL_PLT printf
+ 0: R_ARC_S21H_PCREL_PLT printf
0x[0-9a-f]+ 0800 0002 blne 0x00000000
- 4: ARC_S21W_PCREL_PLT printf
+ 4: R_ARC_S21W_PCREL_PLT printf
0x[0-9a-f]+ 0001 0000 b 0x00000000
- 8: ARC_S25H_PCREL_PLT printf
+ 8: R_ARC_S25H_PCREL_PLT printf
0x[0-9a-f]+ 0802 0000 bl 0x00000000
- c: ARC_S25W_PCREL_PLT printf
+ c: R_ARC_S25W_PCREL_PLT printf
0x[0-9a-f]+ 2700 7f80 0000 0000 add r0,pcl,0
- 14: ARC_PLT32 printf
+ 14: R_ARC_PLT32 printf
0x[0-9a-f]+ 212f 1f8b ffff feff rlc r9,0xfffffeff
0x[0-9a-f]+ 232f 1f8b 4242 4242 rlc r11,0x42424242
0x[0-9a-f]+ 202f 0f8b 0000 0000 rlc r0,0
- 44: ARC_32_ME foo
+ 44: R_ARC_32_ME foo
0x[0-9a-f]+ 202f 804b rlc.f r0,r1
0x[0-9a-f]+ 226f 804b rlc.f r2,0x1
0x[0-9a-f]+ 262f f10b rlc.f 0,r4
0x[0-9a-f]+ 2e03 7080 ffff feff ror r0,0xfffffeff,r2
0x[0-9a-f]+ 2e03 7f80 0000 0100 ror r0,0x100,0x100
0x[0-9a-f]+ 2903 0f80 0000 0000 ror r0,r1,0
- 68: ARC_32_ME foo
+ 68: R_ARC_32_ME foo
0x[0-9a-f]+ 28c3 0080 ror r0,r0,r2
0x[0-9a-f]+ 2bc3 0140 ror r3,r3,r5
0x[0-9a-f]+ 2ec3 0201 ror.eq r6,r6,r8
0x[0-9a-f]+ 212f 1f84 ffff feff rrc r9,0xfffffeff
0x[0-9a-f]+ 232f 1f84 4242 4242 rrc r11,0x42424242
0x[0-9a-f]+ 202f 0f84 0000 0000 rrc r0,0
- 44: ARC_32_ME foo
+ 44: R_ARC_32_ME foo
0x[0-9a-f]+ 202f 8044 rrc.f r0,r1
0x[0-9a-f]+ 226f 8044 rrc.f r2,0x1
0x[0-9a-f]+ 262f f104 rrc.f 0,r4
0x[0-9a-f]+ 2603 7080 ffff feff sbc r0,0xfffffeff,r2
0x[0-9a-f]+ 2603 7f80 0000 0100 sbc r0,0x100,0x100
0x[0-9a-f]+ 2103 0f80 0000 0000 sbc r0,r1,0
- 68: ARC_32_ME foo
+ 68: R_ARC_32_ME foo
0x[0-9a-f]+ 20c3 0080 sbc r0,r0,r2
0x[0-9a-f]+ 23c3 0140 sbc r3,r3,r5
0x[0-9a-f]+ 26c3 0201 sbc.eq r6,r6,r8
Disassembly of section .text:
0x[0-9a-f]+ ce00 add_s r0,gp,0
- 0: ARC_SDA16_LD2 a
+ 0: R_ARC_SDA16_LD2 a
0x[0-9a-f]+ c800 ld_s r0,\[gp,0\]
- 2: ARC_SDA16_LD2 a
+ 2: R_ARC_SDA16_LD2 a
0x[0-9a-f]+ cc00 ldw_s r0,\[gp,0\]
- 4: ARC_SDA16_LD1 a
+ 4: R_ARC_SDA16_LD1 a
0x[0-9a-f]+ ca00 ldb_s r0,\[gp,0\]
- 6: ARC_SDA16_LD a
+ 6: R_ARC_SDA16_LD a
0x[0-9a-f]+ 1200 360c ld.as r12,\[gp\]
- 8: ARC_SDA_LDST2 a
+ 8: R_ARC_SDA_LDST2 a
0x[0-9a-f]+ 1a00 3398 st.as r14,\[gp\]
- c: ARC_SDA_LDST2 a
+ c: R_ARC_SDA_LDST2 a
0x[0-9a-f]+ 1200 300a ld r10,\[gp\]
- 10: ARC_SDA_LDST a
+ 10: R_ARC_SDA_LDST a
0x[0-9a-f]+ 1a00 3240 st r9,\[gp\]
- 14: ARC_SDA_LDST a
+ 14: R_ARC_SDA_LDST a
0x[0-9a-f]+ 1200 3108 ldh r8,\[gp\]
- 18: ARC_SDA_LDST a
+ 18: R_ARC_SDA_LDST a
0x[0-9a-f]+ 1a00 31c4 sth r7,\[gp\]
- 1c: ARC_SDA_LDST a
+ 1c: R_ARC_SDA_LDST a
0x[0-9a-f]+ 1200 3086 ldb r6,\[gp\]
- 20: ARC_SDA_LDST a
+ 20: R_ARC_SDA_LDST a
0x[0-9a-f]+ 1a00 3142 stb r5,\[gp\]
- 24: ARC_SDA_LDST a
+ 24: R_ARC_SDA_LDST a
0x[0-9a-f]+ 1200 3708 ldh.as r8,\[gp\]
- 28: ARC_SDA_LDST1 a
+ 28: R_ARC_SDA_LDST1 a
0x[0-9a-f]+ 1a00 31dc sth.as r7,\[gp\]
- 2c: ARC_SDA_LDST1 a
+ 2c: R_ARC_SDA_LDST1 a
0x[0-9a-f]+ 1200 3688 ldb.as r8,\[gp\]
- 30: ARC_SDA_LDST a
+ 30: R_ARC_SDA_LDST a
0x[0-9a-f]+ 1a00 31da stb.as r7,\[gp\]
- 34: ARC_SDA_LDST a
+ 34: R_ARC_SDA_LDST a
0x[0-9a-f]+ 2200 3f81 0000 0000 add r1,gp,0
- 3c: ARC_SDA32_ME a
+ 3c: R_ARC_SDA32_ME a
Disassembly of section .text:
0x[0-9a-f]+ 1200 3180 ldd r0r1,\[gp\]
- 0: ARC_SDA_LDST b
+ 0: R_ARC_SDA_LDST b
0x[0-9a-f]+ 1a00 3086 std r2r3,\[gp\]
- 4: ARC_SDA_LDST b
+ 4: R_ARC_SDA_LDST b
0x[0-9a-f]+ 1200 3780 ldd.as r0r1,\[gp\]
- 8: ARC_SDA_LDST2 b
+ 8: R_ARC_SDA_LDST2 b
0x[0-9a-f]+ 1a00 309e std.as r2r3,\[gp\]
- c: ARC_SDA_LDST2 b
+ c: R_ARC_SDA_LDST2 b
0x[0-9a-f]+ 5000 ld_s r1,\[gp,0\]
- 10: ARC_SDA16_ST2 b
+ 10: R_ARC_SDA16_ST2 b
0x[0-9a-f]+ 5010 st_s r0,\[gp,0\]
- 12: ARC_SDA16_ST2 b
+ 12: R_ARC_SDA16_ST2 b
0x[0-9a-f]+ 212f 1f85 ffff feff sexb r9,0xfffffeff
0x[0-9a-f]+ 232f 1f85 4242 4242 sexb r11,0x42424242
0x[0-9a-f]+ 202f 0f85 0000 0000 sexb r0,0
- 44: ARC_32_ME foo
+ 44: R_ARC_32_ME foo
0x[0-9a-f]+ 202f 8045 sexb.f r0,r1
0x[0-9a-f]+ 226f 8045 sexb.f r2,0x1
0x[0-9a-f]+ 262f f105 sexb.f 0,r4
0x[0-9a-f]+ 212f 1f86 ffff feff sex[wh]+ r9,0xfffffeff
0x[0-9a-f]+ 232f 1f86 4242 4242 sex[wh]+ r11,0x42424242
0x[0-9a-f]+ 202f 0f86 0000 0000 sex[wh]+ r0,0
- 44: ARC_32_ME foo
+ 44: R_ARC_32_ME foo
0x[0-9a-f]+ 202f 8046 sex[wh]+.f r0,r1
0x[0-9a-f]+ 226f 8046 sex[wh]+.f r2,0x1
0x[0-9a-f]+ 262f f106 sex[wh]+.f 0,r4
1c: 1a00 0003 stb 0,\[r2\]
20: 1af8 8e01 st 56,\[r2,-8\]
24: 1e00 7080 0000 0000 st r2,\[0\]
- 28: ARC_32_ME foo
+ 28: R_ARC_32_ME foo
2c: 1a02 0060 st.di r1,\[r2,2\]
30: 1a03 0068 st.di.aw r1,\[r2,3\]
34: 1a04 006c st[hw]+.di.aw r1,\[r2,4\]
38: 1c04 1f80 0000 0000 st 0,\[r12,4\]
- 3c: ARC_32_ME .L1
+ 3c: R_ARC_32_ME .L1
[0-9a-f]+ <.L1>:
40: 212b 0080 sr r1,\[r2\]
0x[0-9a-f]+ 2602 7080 ffff feff sub r0,0xfffffeff,r2
0x[0-9a-f]+ 2602 7f80 0000 0100 sub r0,0x100,0x100
0x[0-9a-f]+ 2102 0f80 0000 0000 sub r0,r1,0
- 68: ARC_32_ME foo
+ 68: R_ARC_32_ME foo
0x[0-9a-f]+ 20c2 0080 sub r0,r0,r2
0x[0-9a-f]+ 23c2 0140 sub r3,r3,r5
0x[0-9a-f]+ 26c2 0201 sub.eq r6,r6,r8
Disassembly of section .text:
0x[0-9a-f]+ 2730 7f82 0000 0000 ld r2,\[pcl,0\]
- 4: ARC_TLS_IE_GOT var
+ 4: R_ARC_TLS_IE_GOT var
0x[0-9a-f]+ 2700 7f80 0000 0000 add r0,pcl,0
- c: ARC_TLS_GD_GOT var
+ c: R_ARC_TLS_GD_GOT var
0x[0-9a-f]+ 2000 0f81 0000 0000 add r1,r0,0
- 14: ARC_TLS_DTPOFF var
+ 14: R_ARC_TLS_DTPOFF var
0x[0-9a-f]+ 2100 3f80 0000 0000 add r0,r25,0
- 1c: ARC_TLS_LE_32 var
+ 1c: R_ARC_TLS_LE_32 var
0x[0-9a-f]+ 0802 0000 bl 0x00000000
- 20: ARC_TLS_GD_LD .tdata
- 20: ARC_S25W_PCREL_PLT func
+ 20: R_ARC_TLS_GD_LD .tdata
+ 20: R_ARC_S25W_PCREL_PLT func
0x[0-9a-f]+ 2607 7080 ffff feff xor r0,0xfffffeff,r2
0x[0-9a-f]+ 2607 7f80 0000 0100 xor r0,0x100,0x100
0x[0-9a-f]+ 2107 0f80 0000 0000 xor r0,r1,0
- 68: ARC_32_ME foo
+ 68: R_ARC_32_ME foo
0x[0-9a-f]+ 20c7 0080 xor r0,r0,r2
0x[0-9a-f]+ 23c7 0140 xor r3,r3,r5
0x[0-9a-f]+ 26c7 0201 xor.eq r6,r6,r8
projects / external / binutils.git / commitdiff