clk: samsung: add vpll pms tables

This patch adds pms tables to generate various clock frequencies.
In default, VPLL generates 400MHz but it's not enough for MALI GPU
device so it allows to change vpll clock frequency through device tree.

Change-Id: Iae8c55d03a4efc40ecc7966c4591572f27e4a81a
Signed-off-by: Inki Dae <inki.dae@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 7e6f8e6ae91cf8efe70cf6ddcfd69b36a4a971fc..3e691377dc4598aa7c72da0c9b46a62466913a1a 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1300,6 +1300,17 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
        PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719),
 };
 
+static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] __initconst = {
+       PLL_35XX_RATE(600000000U,  100, 2, 1),
+       PLL_35XX_RATE(550000000U,  275, 3, 2),
+       PLL_35XX_RATE(480000000U,  160, 2, 2),
+       PLL_35XX_RATE(420000000U,  140, 2, 2),
+       PLL_35XX_RATE(350000000U,  175, 3, 2),
+       PLL_35XX_RATE(266000000U,  266, 3, 3),
+       PLL_35XX_RATE(177000000U,  118, 2, 3),
+       PLL_35XX_RATE(100000000U,  200, 3, 4),
+};
+
 static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
        [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
                APLL_CON0, NULL),
@@ -1425,6 +1436,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
                exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
                exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
                exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+               exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl;
        }
 
        samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),