mid_pmu: otc ics pmu driver patches ported to umg ics

BZ: 34256

	commit c1e44f12ce693e1e49d409808a1da2de37182142
	Author: Olev Kartau <olev.kartau@intel.com>
	Date:   Thu Mar 15 15:04:03 2012 +0200

	    pmu: interrupt status read value should be signed int

	    u8 status was used to store value from pmu_read_interrupt_status
	    which returns signed int. Comparing u8 to -1 could never match.
	    Also, split status and ret.value to differently typed variables.

	    Signed-off-by: Olev Kartau <olev.kartau@intel.com>
	    Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
	commit b123e410c7ae3019b2eecc7c7549002be559d45a
	Author: Austin Zhang <austin.zhang@intel.com>
	Date:   Thu Feb 23 09:23:53 2012 -0800

	    KER-106: avoid s0i1-idle hang

	    Prevent re-entrant S0i1, just like we do for S0i3;
	    and thus avoid a system hang with S0i1 enabled.

	    https://sa.otcshare.org/jira/browse/KER-106

	    With this patch in place, and loglevel 15
	    (which works around GRA-27), S0i1 has never
	    been observed to hang during over-night testing.

	    Signed-off-by: Austin Zhang <austin.zhang@intel.com>
	    Tested-by: Yong Wang <yong.y.wang@intel.com
	    Tested-by: Kristen C. Accardi <kristen.c.accardi@intel.com>
	    Signed-off-by: Len Brown <len.brown@intel.com>
	    Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Change-Id: I3932e333ce123d1cf5d7e2dd8b80c258e872633e
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
Reviewed-on: http://android.intel.com:8080/48298
Reviewed-by: Hogander, Jouni <jouni.hogander@intel.com>
Reviewed-by: Gross, Mark <mark.gross@intel.com>
Reviewed-by: Popescu, CatalinX <catalinx.popescu@intel.com>
Tested-by: Martin, LoicX <loicx.martin@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>

diff --git a/arch/x86/platform/intel-mid/intel_soc_clv.c b/arch/x86/platform/intel-mid/intel_soc_clv.c
index 73085d6..fb77f03 100644 (file)
--- a/arch/x86/platform/intel-mid/intel_soc_clv.c
+++ b/arch/x86/platform/intel-mid/intel_soc_clv.c
@@ -70,7 +70,7 @@ static void clv_pmu_wakeup(void)
 {
 
        /* Wakeup allother CPU's */
-       if (mid_pmu_cxt->s0ix_entered == MID_S0I3_STATE)
+       if (mid_pmu_cxt->s0ix_entered)
                apic->send_IPI_allbutself(RESCHEDULE_VECTOR);
 }
 

diff --git a/arch/x86/platform/intel-mid/intel_soc_mdfld.c b/arch/x86/platform/intel-mid/intel_soc_mdfld.c
index 60a6347..24176be 100644 (file)
--- a/arch/x86/platform/intel-mid/intel_soc_mdfld.c
+++ b/arch/x86/platform/intel-mid/intel_soc_mdfld.c
@@ -112,7 +112,7 @@ static void mfld_pmu_wakeup(void)
 {
 
        /* Wakeup allother CPU's */
-       if (mid_pmu_cxt->s0ix_entered == MID_S0I3_STATE)
+       if (mid_pmu_cxt->s0ix_entered)
                apic->send_IPI_allbutself(RESCHEDULE_VECTOR);
 
        clear_c6offload_bit();

diff --git a/arch/x86/platform/intel-mid/intel_soc_pm_debug.c b/arch/x86/platform/intel-mid/intel_soc_pm_debug.c
index a54c740..bc691bf 100644 (file)
--- a/arch/x86/platform/intel-mid/intel_soc_pm_debug.c
+++ b/arch/x86/platform/intel-mid/intel_soc_pm_debug.c
@@ -54,7 +54,7 @@ static void pmu_log_timestamp(struct timespec *ts)
        }
 }
 
-void pmu_log_pmu_irq(u8 status, bool interactive_cmd_sent)
+void pmu_log_pmu_irq(int status, bool interactive_cmd_sent)
 {
        struct mid_pmu_pmu_irq_log *log =
                &mid_pmu_cxt->pmu_irq_log[mid_pmu_cxt->pmu_irq_log_idx];
@@ -209,7 +209,7 @@ void pmu_dump_logs(void)
        pmu_dump_ipc_irq_log();
 }
 #else
-void pmu_log_pmu_irq(u8 status, bool interactive_cmd_sent) {}
+void pmu_log_pmu_irq(int status, bool interactive_cmd_sent) {}
 void pmu_log_command(u32 command, struct pmu_ss_states *pm_ssc) {}
 void pmu_dump_logs(void) {}
 #endif /* LOG_PMU_EVENTS */

diff --git a/arch/x86/platform/intel-mid/intel_soc_pmu.c b/arch/x86/platform/intel-mid/intel_soc_pmu.c
index 5abfd95..de22403 100644 (file)
--- a/arch/x86/platform/intel-mid/intel_soc_pmu.c
+++ b/arch/x86/platform/intel-mid/intel_soc_pmu.c
@@ -557,12 +557,13 @@ ret:
  */
 static irqreturn_t pmu_sc_irq(int irq, void *ignored)
 {
-       u8 status = IRQ_NONE;
+       int status;
+       irqreturn_t ret = IRQ_NONE;
        int wake_source;
 
        /* check if interrup pending bit is set, if not ignore interrupt */
        if (unlikely(!pmu_interrupt_pending())) {
-               pmu_log_pmu_irq(status, mid_pmu_cxt->interactive_cmd_sent);
+               pmu_log_pmu_irq(PMU_FAILED, mid_pmu_cxt->interactive_cmd_sent);
                goto ret_no_clear;
        }
 
@@ -574,7 +575,6 @@ static irqreturn_t pmu_sc_irq(int irq, void *ignored)
        switch (status) {
        case INVALID_INT:
                pmu_log_pmu_irq(status, mid_pmu_cxt->interactive_cmd_sent);
-               status = IRQ_NONE;
                goto ret_no_clear;
 
        case CMD_COMPLETE_INT:
@@ -624,9 +624,9 @@ static irqreturn_t pmu_sc_irq(int irq, void *ignored)
                up(&mid_pmu_cxt->scu_ready_sem);
        }
 
-       status = IRQ_HANDLED;
+       ret = IRQ_HANDLED;
 ret_no_clear:
-       return status;
+       return ret;
 }
 
 void pmu_set_s0ix_complete(void)
@@ -636,16 +636,16 @@ void pmu_set_s0ix_complete(void)
 }
 EXPORT_SYMBOL(pmu_set_s0ix_complete);
 
-bool pmu_is_s0i3_in_progress(void)
+bool pmu_is_s0ix_in_progress(void)
 {
        bool state = false;
 
-       if (pmu_initialized && mid_pmu_cxt->s0ix_entered == MID_S0I3_STATE)
+       if (pmu_initialized && mid_pmu_cxt->s0ix_entered)
                state = true;
 
        return state;
 }
-EXPORT_SYMBOL(pmu_is_s0i3_in_progress);
+EXPORT_SYMBOL(pmu_is_s0ix_in_progress);
 
 static inline u32 find_index_in_hash(struct pci_dev *pdev, int *found)
 {

diff --git a/arch/x86/platform/intel-mid/intel_soc_pmu.h b/arch/x86/platform/intel-mid/intel_soc_pmu.h
index 5904c26..e9278eb 100644 (file)
--- a/arch/x86/platform/intel-mid/intel_soc_pmu.h
+++ b/arch/x86/platform/intel-mid/intel_soc_pmu.h
@@ -367,7 +367,7 @@ extern struct platform_pmu_ops *pmu_ops;
 extern u32 get_s0ix_val_set_pm_ssc(int);
 
 #ifdef LOG_PMU_EVENTS
-extern void pmu_log_pmu_irq(u8 status, bool interactive_cmd_sent);
+extern void pmu_log_pmu_irq(int status, bool interactive_cmd_sent);
 extern void pmu_log_command(u32 command, struct pmu_ss_states *pm_ssc);
 extern void pmu_dump_logs(void);
 #endif

diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index ca0b16e..1c2c5e8 100644 (file)
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -302,7 +302,7 @@ static void enter_s0ix_state(u32 eax, int s0ix_state,
                 s0ix_state) {
                s0ix_entered = mid_s0ix_enter(s0ix_state);
                if (!s0ix_entered) {
-                       if (pmu_is_s0i3_in_progress()) {
+                       if (pmu_is_s0ix_in_progress()) {
                                atomic_dec(&nr_cpus_in_c6);
                                eax = C4_HINT;
                        }
@@ -362,11 +362,11 @@ static int soc_s0ix_idle(struct cpuidle_device *dev,
        int cpu = smp_processor_id();
        int s0ix_state   = 0;
 
-       /* Check if s0i3 is already in progress,
+       /* Check if s0ix is already in progress,
         * This is required to demote C6 while S0ix
         * is in progress
         */
-       if (unlikely(pmu_is_s0i3_in_progress())) {
+       if (unlikely(pmu_is_s0ix_in_progress())) {
                dev->last_state = &dev->states[C4_STATE_IDX];
                return intel_idle(dev, &dev->states[C4_STATE_IDX]);
        }

diff --git a/include/linux/intel_mid_pm.h b/include/linux/intel_mid_pm.h
index bc8aca0..c7065ce 100644 (file)
--- a/include/linux/intel_mid_pm.h
+++ b/include/linux/intel_mid_pm.h
@@ -112,7 +112,7 @@ extern pci_power_t pmu_pci_choose_state(struct pci_dev *pdev);
 
 extern void pmu_power_off(void);
 extern void pmu_set_s0ix_complete(void);
-extern bool pmu_is_s0i3_in_progress(void);
+extern bool pmu_is_s0ix_in_progress(void);
 extern int pmu_nc_set_power_state
        (int islands, int state_type, int reg_type);
 extern int mid_nc_read32(u32 cmd, u32 *data);