ARM: uniphier: rename DTCR_RNKEN_* register bit to DTCR_RANKEN_*

The bit 27-24 of the DTCR register is described as RANKEN in the
DDR PHY databook.  Follow this abbreviation.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c b/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c
index f1a2341..b4d369a 100644 (file)
--- a/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c
+++ b/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c
@@ -32,8 +32,8 @@ void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
        /* Use Multi-Purpose Register for DQS gate training */
        tmp |= DTCR_DTMPR;
        /* Specify the rank enabled for data-training */
-       tmp &= ~DTCR_RNKEN_MASK;
-       tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK;
+       tmp &= ~DTCR_RANKEN_MASK;
+       tmp |= (1 << (DTCR_RANKEN_SHIFT + rank)) & DTCR_RANKEN_MASK;
        writel(tmp, p);
 }
 

diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
index adcc972..0c3b508 100644 (file)
--- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
@@ -147,8 +147,8 @@ struct ddrphy {
 #define DTCR_DTRANK_SHIFT      4               /* Data Training Rank */
 #define DTCR_DTRANK_MASK       (0x3 << (DTCR_DTRANK_SHIFT))
 #define DTCR_DTMPR             (1 << 6)        /* Data Training using MPR */
-#define DTCR_RNKEN_SHIFT       24              /* Rank Enable */
-#define DTCR_RNKEN_MASK                (0xf << (DTCR_RNKEN_SHIFT))
+#define DTCR_RANKEN_SHIFT      24              /* Rank Enable */
+#define DTCR_RANKEN_MASK       (0xf << (DTCR_RANKEN_SHIFT))
 
 #define DXGCR_WLRKEN_SHIFT     26              /* Write Level Rank Enable */
 #define DXGCR_WLRKEN_MASK      (0xf << (DXGCR_WLRKEN_SHIFT))