drm/i915: There is only one fault register from GEN8 onwards

Until Haswell/Baytrail, the hardware used to have a per engine fault
register (e.g. 0x4094 - render fault register, 0x4194 - media fault
register and so on). But since Broadwell, all these registers were
combined into a singe one and the engine id stored in bits 14:12.

Not only we should not been reading (and writing to) registers that do
not exist, in platforms with VCS2 (SKL), the address that would belong
this engine (0x4494, VCS2_HW = 4) is already assigned to other register.

v2: use less controversial function names (Chris).
v3: make non-exported functions static, remove now obsolete check for
engine presence before posting_read (Chris).

References: IHD-OS-BDW-Vol 2c-11.15, page 75.
References: IHD-OS-SKL-Vol 2c-05.16, page 350.
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171113173628.11689-1-michel.thierry@intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 1e40eeb..3c3a699 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2256,35 +2256,62 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv)
        return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active();
 }
 
-void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
+static void gen6_check_and_clear_faults(struct drm_i915_private *dev_priv)
 {
        struct intel_engine_cs *engine;
        enum intel_engine_id id;
-
-       if (INTEL_INFO(dev_priv)->gen < 6)
-               return;
+       u32 fault;
 
        for_each_engine(engine, dev_priv, id) {
-               u32 fault_reg;
-               fault_reg = I915_READ(RING_FAULT_REG(engine));
-               if (fault_reg & RING_FAULT_VALID) {
+               fault = I915_READ(RING_FAULT_REG(engine));
+               if (fault & RING_FAULT_VALID) {
                        DRM_DEBUG_DRIVER("Unexpected fault\n"
                                         "\tAddr: 0x%08lx\n"
                                         "\tAddress space: %s\n"
                                         "\tSource ID: %d\n"
                                         "\tType: %d\n",
-                                        fault_reg & PAGE_MASK,
-                                        fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
-                                        RING_FAULT_SRCID(fault_reg),
-                                        RING_FAULT_FAULT_TYPE(fault_reg));
+                                        fault & PAGE_MASK,
+                                        fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
+                                        RING_FAULT_SRCID(fault),
+                                        RING_FAULT_FAULT_TYPE(fault));
                        I915_WRITE(RING_FAULT_REG(engine),
-                                  fault_reg & ~RING_FAULT_VALID);
+                                  fault & ~RING_FAULT_VALID);
                }
        }
 
-       /* Engine specific init may not have been done till this point. */
-       if (dev_priv->engine[RCS])
-               POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
+       POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
+}
+
+static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv)
+{
+       u32 fault = I915_READ(GEN8_RING_FAULT_REG);
+
+       if (fault & RING_FAULT_VALID) {
+               DRM_DEBUG_DRIVER("Unexpected fault\n"
+                                "\tAddr: 0x%08lx\n"
+                                "\tEngine ID: %d\n"
+                                "\tSource ID: %d\n"
+                                "\tType: %d\n",
+                                fault & PAGE_MASK,
+                                GEN8_RING_FAULT_ENGINE_ID(fault),
+                                RING_FAULT_SRCID(fault),
+                                RING_FAULT_FAULT_TYPE(fault));
+               I915_WRITE(GEN8_RING_FAULT_REG,
+                          fault & ~RING_FAULT_VALID);
+       }
+
+       POSTING_READ(GEN8_RING_FAULT_REG);
+}
+
+void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
+{
+       /* From GEN8 onwards we only have one 'All Engine Fault Register' */
+       if (INTEL_GEN(dev_priv) >= 8)
+               gen8_check_and_clear_faults(dev_priv);
+       else if (INTEL_GEN(dev_priv) >= 6)
+               gen6_check_and_clear_faults(dev_priv);
+       else
+               return;
 }
 
 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 5c2d83a..7481c8e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1217,11 +1217,13 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
 
        if (INTEL_GEN(dev_priv) >= 6) {
                ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
-               ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
-               if (INTEL_GEN(dev_priv) >= 8)
+               if (INTEL_GEN(dev_priv) >= 8) {
                        gen8_record_semaphore_state(error, engine, ee);
-               else
+                       ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
+               } else {
                        gen6_record_semaphore_state(engine, ee);
+                       ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
+               }
        }
 
        if (INTEL_GEN(dev_priv) >= 4) {

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 05e33a4..e52e74d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2360,6 +2360,8 @@ enum i915_power_well_id {
 #define   ARB_MODE_SWIZZLE_BDW (1<<1)
 #define RENDER_HWS_PGA_GEN7    _MMIO(0x04080)
 #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100*(engine)->hw_id)
+#define GEN8_RING_FAULT_REG    _MMIO(0x4094)
+#define   GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
 #define   RING_FAULT_GTTSEL_MASK (1<<11)
 #define   RING_FAULT_SRCID(x)  (((x) >> 3) & 0xff)
 #define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)