MIPS: Ingenic: Disable abandoned HPTLB function.

JZ4760/JZ4770/JZ4775/X1000/X1500 has an abandoned huge page tlb,
this mode is not compatible with the MIPS standard, it will cause
tlbmiss and into an infinite loop (line 21 in the tlb-funcs.S)
when starting the init process. write 0xa9000000 to cp0 register 5
sel 4 to disable this function to prevent getting stuck. Confirmed
by Ingenic, this operation will not adversely affect processors
without HPTLB function.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Paul Burton <paulburton@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: jiaxun.yang@flygoat.com
Cc: gregkh@linuxfoundation.org
Cc: malat@debian.org
Cc: tglx@linutronix.de
Cc: chenhc@lemote.com

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index bdbdc19..0d5a309 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -689,6 +689,9 @@
 #define MIPS_CONF7_IAR         (_ULCAST_(1) << 10)
 #define MIPS_CONF7_AR          (_ULCAST_(1) << 16)
 
+/* Ingenic HPTLB off bits */
+#define XBURST_PAGECTRL_HPTLB_DIS 0xa9000000
+
 /* Ingenic Config7 bits */
 #define MIPS_CONF7_BTB_LOOP_EN (_ULCAST_(1) << 4)
 
@@ -1971,6 +1974,9 @@ do {                                                                      \
 #define read_c0_brcm_sleepcount()      __read_32bit_c0_register($22, 7)
 #define write_c0_brcm_sleepcount(val)  __write_32bit_c0_register($22, 7, val)
 
+/* Ingenic page ctrl register */
+#define write_c0_page_ctrl(val)        __write_32bit_c0_register($5, 4, val)
+
 /*
  * Macros to access the guest system control coprocessor
  */

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 105d89c..c543326 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1977,13 +1977,30 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
                break;
        }
 
+       switch (c->processor_id & PRID_COMP_MASK) {
+       /*
+        * The config0 register in the XBurst CPUs with a processor ID of
+        * PRID_COMP_INGENIC_D1 has an abandoned huge page tlb mode, this
+        * mode is not compatible with the MIPS standard, it will cause
+        * tlbmiss and into an infinite loop (line 21 in the tlb-funcs.S)
+        * when starting the init process. After chip reset, the default
+        * is HPTLB mode, Write 0xa9000000 to cp0 register 5 sel 4 to
+        * switch back to VTLB mode to prevent getting stuck.
+        */
+       case PRID_COMP_INGENIC_D1:
+               write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
+               break;
        /*
-        * The config0 register in the Xburst CPUs with a processor ID of
+        * The config0 register in the XBurst CPUs with a processor ID of
         * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
         * but they don't actually support this ISA.
         */
-       if ((c->processor_id & PRID_COMP_MASK) == PRID_COMP_INGENIC_D0)
+       case PRID_COMP_INGENIC_D0:
                c->isa_level &= ~MIPS_CPU_ISA_M32R2;
+               break;
+       default:
+               break;
+       }
 }
 
 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)