drm/amdgpu: refine cz uvd clock gate logic.

sw clockgate was used on uvd6.0.
when uvd is idle, we gate the uvd clock.
when decode, we ungate the uvd clock.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index 41fa351..ba2b66b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -2111,9 +2111,8 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
 
        if (gate) {
                if (pi->caps_uvd_pg) {
-                       /* disable clockgating so we can properly shut down the block */
                        ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
-                                                           AMD_CG_STATE_UNGATE);
+                                                           AMD_CG_STATE_GATE);
                        if (ret) {
                                DRM_ERROR("UVD DPM Power Gating failed to set clockgating state\n");
                                return;
@@ -2159,9 +2158,8 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
                                return;
                        }
 
-                       /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
                        ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
-                                                           AMD_CG_STATE_GATE);
+                                                           AMD_CG_STATE_UNGATE);
                        if (ret) {
                                DRM_ERROR("UVD DPM Power Gating Failed to set clockgating state\n");
                                return;

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
index 2028980..b0c63c5 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
@@ -169,7 +169,7 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
        if (bgate) {
                cgs_set_clockgating_state(hwmgr->device,
                                                AMD_IP_BLOCK_TYPE_UVD,
-                                               AMD_CG_STATE_UNGATE);
+                                               AMD_CG_STATE_GATE);
                cgs_set_powergating_state(hwmgr->device,
                                                AMD_IP_BLOCK_TYPE_UVD,
                                                AMD_PG_STATE_GATE);
@@ -182,7 +182,7 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
                                                AMD_CG_STATE_UNGATE);
                cgs_set_clockgating_state(hwmgr->device,
                                                AMD_IP_BLOCK_TYPE_UVD,
-                                               AMD_PG_STATE_GATE);
+                                               AMD_PG_STATE_UNGATE);
                cz_dpm_update_uvd_dpm(hwmgr, false);
        }