AVX-512. Add integer max/min.

gcc/
	* config/i386/sse.md
	(define_mode_iterator VI128_256): New.
	(define_insn "<mask_codefor><code><mode>3<mask_name>"): Ditto.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@214669 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a758ff4..326919a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -8,6 +8,19 @@
            Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 
        * config/i386/sse.md
+       (define_mode_iterator VI128_256): New.
+       (define_insn "<mask_codefor><code><mode>3<mask_name>"): Ditto.
+
+2014-08-28  Alexander Ivchenko  <alexander.ivchenko@intel.com>
+           Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+           Anna Tikhonova  <anna.tikhonova@intel.com>
+           Ilya Tocar  <ilya.tocar@intel.com>
+           Andrey Turetskiy  <andrey.turetskiy@intel.com>
+           Ilya Verbin  <ilya.verbin@intel.com>
+           Kirill Yukhin  <kirill.yukhin@intel.com>
+           Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+       * config/i386/sse.md
        (define_mode_iterator VI8_256_512): New.
        (define_insn "<mask_codefor>avx512dq_cvtps2qq<mode><mask_name><round_name>"):
        Ditto.

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 5904450..6c99d84 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -281,6 +281,9 @@
 (define_mode_iterator VI8_256_512
   [V8DI (V4DI "TARGET_AVX512VL")])
 
+(define_mode_iterator VI128_256
+  [V4DI V2DI V4SI (V16QI "TARGET_AVX512BW") (V8HI "TARGET_AVX512BW")])
+
 (define_mode_iterator VI1_AVX2
   [(V32QI "TARGET_AVX2") V16QI])
 
@@ -8922,6 +8925,17 @@
    (set_attr "prefix" "maybe_evex")
    (set_attr "mode" "OI")])
 
+(define_insn "<mask_codefor><code><mode>3<mask_name>"
+  [(set (match_operand:VI128_256 0 "register_operand" "=v")
+        (maxmin:VI128_256
+          (match_operand:VI128_256 1 "register_operand" "v")
+          (match_operand:VI128_256 2 "nonimmediate_operand" "vm")))]
+  "TARGET_AVX512VL"
+  "vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+  [(set_attr "type" "sseiadd")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "<sseinsnmode>")])
+
 (define_expand "<code><mode>3"
   [(set (match_operand:VI8_AVX2 0 "register_operand")
        (maxmin:VI8_AVX2