ASan build fix: resolve multiple definitions.

Put "extern" to multiply-defined variables in order to make
-fno-common work.

Change-Id: Ib5a882e3c536d868e8098e385823e50ac78f2d21

diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c
index 76f398b..e7ba966 100644 (file)
--- a/sim/arm/armemu.c
+++ b/sim/arm/armemu.c
@@ -1142,7 +1142,7 @@ handle_VFP_move (ARMul_State * state, ARMword instr)
 
 /* The PC pipeline value depends on whether ARM
    or Thumb instructions are being executed.  */
-ARMword isize;
+extern ARMword isize;
 
 ARMword
 #ifdef MODE32

diff --git a/sim/arm/armsupp.c b/sim/arm/armsupp.c
index 11bb53c..a07b162 100644 (file)
--- a/sim/arm/armsupp.c
+++ b/sim/arm/armsupp.c
@@ -22,6 +22,8 @@
 
 /* Definitions for the support routines.  */
 
+ARMword isize;
+
 static ARMword ModeToBank (ARMword);
 static void    EnvokeList (ARMul_State *, unsigned long, unsigned long);
 

diff --git a/sim/arm/maverick.c b/sim/arm/maverick.c
index c112692..c00908c 100644 (file)
--- a/sim/arm/maverick.c
+++ b/sim/arm/maverick.c
@@ -60,9 +60,9 @@ union maverick_acc_regs
   long double ld;              /* Acc registers are 72-bits.  */
 };
 
-struct maverick_regs DSPregs[16];
-union maverick_acc_regs DSPacc[4];
-ARMword DSPsc;
+extern struct maverick_regs DSPregs[16];
+extern union maverick_acc_regs DSPacc[4];
+extern ARMword DSPsc;
 
 #define DEST_REG       (BITS (12, 15))
 #define SRC1_REG       (BITS (16, 19))