case AArch64::LDRWpre:
case AArch64::LDURXi:
case AArch64::LDRXpre:
+ case AArch64::LDRSWpre:
case AArch64::LDURSWi:
case AArch64::LDURHHi:
case AArch64::LDURBBi:
case AArch64::LDURXi:
case AArch64::LDRXpre:
case AArch64::LDURSWi:
+ case AArch64::LDRSWpre:
return true;
}
}
// Can't merge/pair if the instruction modifies the base register.
// e.g., ldr x0, [x0]
// This case will never occur with an FI base.
- // However, if the instruction is an LDR/STR<S,D,Q,W,X>pre, it can be merged.
+ // However, if the instruction is an LDR<S,D,Q,W,X,SW>pre or
+ // STR<S,D,Q,W,X>pre, it can be merged.
// For example:
// ldr q0, [x11, #32]!
// ldr q1, [x11, #16]
case AArch64::LDRSpre:
case AArch64::LDRSWui:
case AArch64::LDURSWi:
+ case AArch64::LDRSWpre:
case AArch64::LDRWpre:
case AArch64::LDRWui:
case AArch64::LDURWi:
return false;
case AArch64::LDRWpre:
case AArch64::LDRXpre:
+ case AArch64::LDRSWpre:
case AArch64::LDRSpre:
case AArch64::LDRDpre:
case AArch64::LDRQpre:
return AArch64::LDRWui;
case AArch64::LDURSWi:
return AArch64::LDURWi;
+ case AArch64::LDRSWpre:
+ return AArch64::LDRWpre;
}
}
case AArch64::LDRSWui:
case AArch64::LDURSWi:
return AArch64::LDPSWi;
+ case AArch64::LDRSWpre:
+ return AArch64::LDPSWpre;
}
}
return (OpcB == AArch64::LDRWui) || (OpcB == AArch64::LDURWi);
case AArch64::LDRXpre:
return (OpcB == AArch64::LDRXui) || (OpcB == AArch64::LDURXi);
+ case AArch64::LDRSWpre:
+ return (OpcB == AArch64::LDRSWui) || (OpcB == AArch64::LDURSWi);
}
}
return false;
// The STR<S,D,Q,W,X>pre - STR<S,D,Q,W,X>ui and
- // LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui
+ // LDR<S,D,Q,W,X,SW>pre-LDR<S,D,Q,W,X,SW>ui
// are candidate pairs that can be merged.
if (isPreLdStPairCandidate(FirstMI, MI))
return true;
---
-name: 21-ldrswpre-ldrswui-no-merge
+name: 21-ldrswpre-ldrswui-merge
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
body: |
bb.0:
liveins: $x0, $x1, $x2
- ; CHECK-LABEL: name: 21-ldrswpre-ldrswui-no-merge
+ ; CHECK-LABEL: name: 21-ldrswpre-ldrswui-merge
; CHECK: liveins: $x0, $x1, $x2
- ; CHECK: early-clobber renamable $x1, renamable $x0 = LDRSWpre renamable $x1, 40, implicit $w1 :: (load (s32))
- ; CHECK: renamable $x2 = LDRSWui renamable $x1, 1 :: (load (s32))
+ ; CHECK: early-clobber $x1, renamable $x0, renamable $x2 = LDPSWpre renamable $x1, 10 :: (load (s32))
; CHECK: STPXi renamable $x0, renamable $x2, renamable $x1, 0 :: (store (s64))
; CHECK: RET undef $lr
early-clobber renamable $x1, renamable $x0 = LDRSWpre killed renamable $x1, 40 :: (load (s32))
---
-name: 22-ldrswpre-ldurswi-no-merge
+name: 22-ldrswpre-ldurswi-merge
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
body: |
bb.0:
liveins: $x0, $x1, $x2
- ; CHECK-LABEL: name: 22-ldrswpre-ldurswi-no-merge
+ ; CHECK-LABEL: name: 22-ldrswpre-ldurswi-merge
; CHECK: liveins: $x0, $x1, $x2
- ; CHECK: early-clobber renamable $x1, renamable $x0 = LDRSWpre renamable $x1, 40, implicit $w1 :: (load (s32))
- ; CHECK: renamable $x2 = LDURSWi renamable $x1, 4 :: (load (s32))
+ ; CHECK: early-clobber $x1, renamable $x0, renamable $x2 = LDPSWpre renamable $x1, 10 :: (load (s32))
; CHECK: STPXi renamable $x0, renamable $x2, renamable $x1, 0 :: (store (s64))
; CHECK: RET undef $lr
early-clobber renamable $x1, renamable $x0 = LDRSWpre killed renamable $x1, 40 :: (load (s32))