},
};
+#define INTER_MODE_MASK 0x03
+#define INTER_8X8 0x03
+#define SUBMB_SHAPE_MASK 0x00FF00
+
+#define INTER_MV8 (4 << 20)
+#define INTER_MV32 (6 << 20)
+
+
static void
gen75_mfc_pipe_mode_select(VADriverContextP ctx,
int standard_select,
(0 << 13) | /* CABAC 0 word insertion test enable */
(1 << 12) | /* MVUnpackedEnable,compliant to DXVA */
(1 << 10) | /* Chroma Format IDC, 4:2:0 */
- (0 << 9) | /* FIXME: MbMvFormatFlag */
+ (0 << 8) | /* FIXME: MbMvFormatFlag */
(pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7) | /*0:CAVLC encoding mode,1:CABAC*/
(0 << 6) | /* Only valid for VLD decoding mode */
(0 << 5) | /* Constrained Intra Predition Flag, from PPS */
struct intel_batchbuffer *batch)
{
int len_in_dwords = 11;
-
+ unsigned int inter_msg = 0;
if (batch == NULL)
batch = encoder_context->base.batch;
OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
- OUT_BCS_BATCH(batch, msg[2]); /* 32 MV*/
+ inter_msg = 32;
+ /* MV quantity */
+ if ((msg[0] & INTER_MODE_MASK) == INTER_8X8) {
+ if (msg[1] & SUBMB_SHAPE_MASK)
+ inter_msg = 128;
+ }
+ OUT_BCS_BATCH(batch, inter_msg); /* 32 MV*/
OUT_BCS_BATCH(batch, offset);
+ inter_msg = msg[0] & (0x1F00FFFF);
+ inter_msg |= INTER_MV8;
+ if (((msg[0] & INTER_MODE_MASK) == INTER_8X8) &&
+ (msg[1] & SUBMB_SHAPE_MASK)) {
+ inter_msg |= INTER_MV32;
+ }
- OUT_BCS_BATCH(batch, msg[0]);
+ OUT_BCS_BATCH(batch, inter_msg);
OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/
OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */
#endif
-
+ inter_msg = msg[1] >> 8;
/*Stuff for Inter MB*/
- OUT_BCS_BATCH(batch, msg[1]);
+ OUT_BCS_BATCH(batch, inter_msg);
OUT_BCS_BATCH(batch, 0x0);
OUT_BCS_BATCH(batch, 0x0);
return len_in_dwords;
}
+#define INTRA_RDO_OFFSET 4
+#define INTER_RDO_OFFSET 54
+#define INTER_MSG_OFFSET 52
+#define INTER_MV_OFFSET 224
+#define RDO_MASK 0xFFFF
+
static void
gen75_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
struct encode_state *encode_state,
msg = (unsigned int *) (msg_ptr + pSliceParameter->macroblock_address * vme_context->vme_output.size_block);
} else {
msg = (unsigned int *) (msg_ptr + pSliceParameter->macroblock_address * vme_context->vme_output.size_block);
- msg += 32; /* the first 32 DWs are MVs */
- offset = pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_BYTES;
}
for (i = pSliceParameter->macroblock_address;
assert(msg);
gen75_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
} else {
- if (msg[0] & INTRA_MB_FLAG_MASK) {
+ int inter_rdo, intra_rdo;
+ inter_rdo = msg[INTER_RDO_OFFSET] & RDO_MASK;
+ intra_rdo = msg[INTRA_RDO_OFFSET] & RDO_MASK;
+ offset = i * vme_context->vme_output.size_block + INTER_MV_OFFSET;
+ if (intra_rdo < inter_rdo) {
gen75_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
} else {
+ msg += INTER_MSG_OFFSET;
gen75_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, pSliceParameter->slice_type, slice_batch);
}
-
- offset += INTER_VME_OUTPUT_IN_BYTES;
}
}
};
static const uint32_t gen75_vme_inter_frame[][4] = {
-#include "shaders/vme/inter_frame.g7b"
+#include "shaders/vme/inter_frame_haswell.g75b"
};
static const uint32_t gen75_vme_batchbuffer[][4] = {
if (is_intra)
vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 2;
else
- vme_context->vme_output.size_block = INTER_VME_OUTPUT_IN_BYTES;
+ vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 24;
+ /*
+ * Inter MV . 32-byte Intra search + 16 IME info + 128 IME MV + 32 IME Ref
+ * + 16 FBR Info + 128 FBR MV + 32 FBR Ref.
+ * 16 * (2 + 2 * (1 + 8 + 2))= 16 * 24.
+ */
vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
"VME output buffer",
VME_CORE = batchbuffer.asm intra_frame.asm inter_frame.asm
-VME75_CORE = batchbuffer.asm intra_frame_haswell.asm
+VME75_CORE = batchbuffer.asm intra_frame_haswell.asm inter_frame_haswell.asm
INTEL_G6B = batchbuffer.g6b intra_frame.g6b inter_frame.g6b
INTEL_G6A = batchbuffer.g6a intra_frame.g6a inter_frame.g6a
INTEL_GEN7_INC = batchbuffer.inc vme.inc
INTEL_GEN7_ASM = $(INTEL_G7A:%.g7a=%.gen7.asm)
-INTEL_G75B = batchbuffer.g75b intra_frame_haswell.g75b
-INTEL_G75A = batchbuffer.g75a intra_frame_haswell.g75a
+INTEL_G75B = batchbuffer.g75b intra_frame_haswell.g75b inter_frame_haswell.g75b
+INTEL_G75A = batchbuffer.g75a intra_frame_haswell.g75a inter_frame_haswell.g75a
INTEL_GEN75_INC = batchbuffer.inc vme75.inc
INTEL_GEN75_ASM = $(INTEL_G75A:%.g75a=%.gen75.asm)
--- /dev/null
+/*
+ * Copyright © <2010>, Intel Corporation.
+ *
+ * This program is licensed under the terms and conditions of the
+ * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at
+ * http://www.opensource.org/licenses/eclipse-1.0.php.
+ *
+ */
+// Modual name: IntraFrame.asm
+//
+// Make intra predition estimation for Intra frame
+//
+
+//
+// Now, begin source code....
+//
+
+/*
+ * __START
+ */
+__INTRA_START:
+mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1};
+mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1};
+mov (16) tmp_reg4.0<1>:UD 0x0:UD {align1} ;
+mov (16) tmp_reg6.0<1>:UD 0x0:UD {align1} ;
+
+shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */
+add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */
+add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */
+mov (1) read0_header.8<1>:UD BLOCK_32X1 {align1};
+mov (1) read0_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */
+
+shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */
+add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */
+mov (1) read1_header.8<1>:UD BLOCK_4X16 {align1};
+mov (1) read1_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */
+
+shl (2) vme_m0.8<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */
+mov (1) vme_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
+
+mul (1) obw_m0.8<1>:UD w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1};
+add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1};
+mul (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 24:UD {align1};
+mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
+
+/*
+ * Media Read Message -- fetch Luma neighbor edge pixels
+ */
+/* ROW */
+mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1};
+send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1};
+
+/* COL */
+mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1};
+send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1};
+
+/*
+ * Media Read Message -- fetch Chroma neighbor edge pixels
+ */
+/* ROW */
+shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 3:UW {align1}; /* x * 16 , y * 8 */
+mul (1) read0_header.0<1>:D read0_header.0<0,1,0>:D 2:W {align1};
+add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */
+add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */
+mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1};
+send (8) msg_ind CHROMA_ROW<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1};
+
+/* COL */
+shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 3:UW {align1}; /* x * 16, y * 8 */
+mul (1) read1_header.0<1>:D read1_header.0<0,1,0>:D 2:W {align1};
+add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */
+mov (1) read1_header.8<1>:UD BLOCK_8X4 {align1};
+mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1};
+send (8) msg_ind CHROMA_COL<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1};
+
+/* m2, get the MV/Mb cost passed from constant buffer when
+spawning thread by MEDIA_OBJECT */
+mov (8) vme_m2<1>:UD r1.0<8,8,1>:UD {align1};
+
+mov (8) vme_msg_2<1>:UD vme_m2.0<8,8,1>:UD {align1};
+
+/* m3 */
+mov (8) vme_msg_3<1>:UD 0x0:UD {align1};
+
+/* m4 */
+mov (1) INEP_ROW.0<1>:UD 0x0:UD {align1};
+and (1) INEP_ROW.4<1>:UD INEP_ROW.4<0,1,0>:UD 0xFF000000:UD {align1};
+mov (8) vme_msg_4<1>:UD INEP_ROW.0<8,8,1>:UD {align1};
+
+/* m5 */
+mov (8) vme_msg_5<1>:UD 0x0:UD {align1};
+mov (16) vme_msg_5.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1};
+mov (1) vme_msg_5.16<1>:UD INTRA_PREDICTORE_MODE {align1};
+
+/* the penalty for Intra mode */
+mov (1) vme_msg_5.28<1>:UD 0x010101:UD {align1};
+mov (1) vme_msg_5.20<1>:UW CHROMA_ROW.6<0,1,0>:UW {align1};
+
+
+/* m6 */
+
+mov (4) vme_msg_6.16<1>:UD CHROMA_ROW.8<4,4,1>:UD {align1};
+mov (8) vme_msg_6.0<1>:UW CHROMA_COL.2<16,8,2>:UW {align1};
+
+/*
+ * SIC VME message
+ */
+/* m0 */
+mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1};
+mov (1) tmp_reg0.0<1>:UW LUMA_INTRA_MODE:UW {align1};
+/* Use the Luma mode */
+mov (1) vme_msg_4.5<1>:UB tmp_reg0.0<0,1,0>:UB {align1};
+
+/* m1 */
+mov (1) intra_flag<1>:UW 0x0:UW {align1} ;
+and.z.f0.0 (1) null<1>:UW transform_8x8_ub<0,1,0>:UB 1:UW {align1};
+(f0.0) mov (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE {align1};
+
+cmp.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB 0:UW {align1}; /* X != 0 */
+(f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_AE {align1}; /* A */
+
+cmp.nz.f0.0 (1) null<1>:UW orig_y_ub<0,1,0>:UB 0:UW {align1}; /* Y != 0 */
+(f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_B {align1}; /* B */
+
+mul.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB orig_y_ub<0,1,0>:UB {align1}; /* X * Y != 0 */
+(f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_D {align1}; /* D */
+
+add (1) tmp_x_w<1>:W orig_x_ub<0,1,0>:UB 1:UW {align1}; /* X + 1 */
+add (1) tmp_x_w<1>:W w_in_mb_uw<0,1,0>:UW -tmp_x_w<0,1,0>:W {align1}; /* width - (X + 1) */
+mul.nz.f0.0 (1) null<1>:UD tmp_x_w<0,1,0>:W orig_y_ub<0,1,0>:UB {align1}; /* (width - (X + 1)) * Y != 0 */
+(f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_C {align1}; /* C */
+
+and.nz.f0.0 (1) null<1>:UW slice_edge_ub<0,1,0>:UB 2:UW {align1};
+(f0.0) and (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB 0xE0 {align1}; /* slice edge disable B,C,D*/
+
+/* Disable DC HAAR component when calculating HARR SATD block */
+mov (1) tmp_reg0.0<1>:UW DC_HARR_DISABLE:UW {align1};
+mov (1) vme_m1.30<1>:UB tmp_reg0.0<0,1,0>:UB {align1};
+
+mov (1) vme_m0.12<1>:UD INTRA_SAD_HAAR:UD {align1}; /* 16x16 Source, Intra_harr */
+/* m0 */
+mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1};
+mov (8) vme_msg_1<1>:UD vme_m1.0<8,8,1>:UD {align1};
+
+/* after verification it will be passed by using payload */
+send (8)
+ vme_msg_ind
+ vme_wb<1>:UD
+ null
+ cre(
+ BIND_IDX_VME,
+ VME_SIC_MESSAGE_TYPE
+ )
+ mlen sic_vme_msg_length
+ rlen vme_wb_length
+ {align1};
+/*
+ * Oword Block Write message
+ */
+mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1};
+
+mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1};
+mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1};
+mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1};
+mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1};
+
+/* Distortion, Intra (17-16), */
+mov (1) msg_reg1.16<1>:UW vme_wb.12<0,1,0>:UW {align1};
+
+mov (1) msg_reg1.20<1>:UD vme_wb.8<0,1,0>:UD {align1};
+/* VME clock counts */
+mov (1) msg_reg1.24<1>:UD vme_wb.28<0,1,0>:UD {align1};
+
+mov (1) msg_reg1.28<1>:UD obw_m0.8<0,1,0>:UD {align1};
+
+/* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */
+send (16)
+ msg_ind
+ obw_wb
+ null
+ data_port(
+ OBW_CACHE_TYPE,
+ OBW_MESSAGE_TYPE,
+ OBW_CONTROL_2,
+ OBW_BIND_IDX,
+ OBW_WRITE_COMMIT_CATEGORY,
+ OBW_HEADER_PRESENT
+ )
+ mlen 2
+ rlen obw_wb_length
+ {align1};
+
+/* IME search */
+mov (1) vme_m0.12<1>:UD SEARCH_CTRL_SINGLE + INTER_PART_MASK + INTER_SAD_HAAR:UD {align1}; /* 16x16 Source, harr */
+mov (1) vme_m0.22<1>:UW REF_REGION_SIZE {align1}; /* Reference Width&Height, 48x40 */
+
+mov (1) vme_m0.0<1>:UD vme_m0.8<0,1,0>:UD {align1};
+
+add (1) vme_m0.0<1>:W vme_m0.0<0,1,0>:W -16:W {align1}; /* Reference = (x-16,y-12)-(x+32,y+28) */
+add (1) vme_m0.2<1>:W vme_m0.2<0,1,0>:W -12:W {align1};
+
+mov (1) vme_m0.0<1>:W -16:W {align1};
+mov (1) vme_m0.2<1>:W -12:W {align1};
+
+mov (1) vme_m0.4<1>:UD vme_m0.0<0,1,0>:UD {align1};
+
+mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1};
+
+mov (1) vme_m1.0<1>:UD ADAPTIVE_SEARCH_ENABLE:ud {align1} ;
+mov (1) vme_m1.4<1>:UD MAX_NUM_MV:UD {align1}; /* Default value MAX 32 MVs */
+mov (1) vme_m1.8<1>:UD START_CENTER + SEARCH_PATH_LEN:UD {align1};
+mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1};
+
+mov (8) vme_msg_2<1>:UD vme_m2.0<8,8,1>:UD {align1};
+/* M3/M4 search path */
+
+mov (1) vme_msg_3.0<1>:UD 0x01010101:UD {align1};
+mov (1) vme_msg_3.4<1>:UD 0x10010101:UD {align1};
+mov (1) vme_msg_3.8<1>:UD 0x0F0F0F0F:UD {align1};
+mov (1) vme_msg_3.12<1>:UD 0x100F0F0F:UD {align1};
+mov (1) vme_msg_3.16<1>:UD 0x01010101:UD {align1};
+mov (1) vme_msg_3.20<1>:UD 0x10010101:UD {align1};
+mov (1) vme_msg_3.24<1>:UD 0x0F0F0F0F:UD {align1};
+mov (1) vme_msg_3.28<1>:UD 0x100F0F0F:UD {align1};
+
+mov (1) vme_msg_4.0<1>:UD 0x01010101:UD {align1};
+mov (1) vme_msg_4.4<1>:UD 0x10010101:UD {align1};
+mov (1) vme_msg_4.8<1>:UD 0x0F0F0F0F:UD {align1};
+mov (1) vme_msg_4.12<1>:UD 0x000F0F0F:UD {align1};
+
+mov (4) vme_msg_4.16<1>:UD 0x0:UD {align1};
+
+send (8)
+ vme_msg_ind
+ vme_wb<1>:UD
+ null
+ vme(
+ BIND_IDX_VME,
+ 0,
+ 0,
+ VME_IME_MESSAGE_TYPE
+ )
+ mlen ime_vme_msg_length
+ rlen vme_wb_length {align1};
+
+/* Set Macroblock-shape/mode for FBR */
+
+mov (1) vme_m2.20<1>:UD 0x0:UD {align1};
+mov (1) vme_m2.21<1>:UB vme_wb.25<0,1,0>:UB {align1};
+mov (1) vme_m2.22<1>:UB vme_wb.26<0,1,0>:UB {align1};
+
+and (1) tmp_reg0.0<1>:UW vme_wb.0<0,1,0>:UW 0x03:UW {align1};
+mov (1) vme_m2.20<1>:UB tmp_reg0.0<0,1,0>:UB {align1};
+
+/* Write IME inter info */
+add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x02:UD {align1};
+mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1};
+
+mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1};
+
+mov (1) msg_reg1.4<1>:UD vme_wb.24<0,1,0>:UD {align1};
+/* Inter distortion of IME */
+mov (1) msg_reg1.8<1>:UD vme_wb.8<0,1,0>:UD {align1};
+
+mov (1) msg_reg1.12<1>:UD obw_m0.8<0,1,0>:UD {align1};
+
+/* bind index 3, write oword (16bytes), msg type: 8(OWord Block Write) */
+send (16)
+ msg_ind
+ obw_wb
+ null
+ data_port(
+ OBW_CACHE_TYPE,
+ OBW_MESSAGE_TYPE,
+ OBW_CONTROL_0,
+ OBW_BIND_IDX,
+ OBW_WRITE_COMMIT_CATEGORY,
+ OBW_HEADER_PRESENT
+ )
+ mlen 2
+ rlen obw_wb_length
+ {align1};
+
+/* Write IME MV */
+add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x01:UD {align1};
+mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1};
+
+mov (8) msg_reg1.0<1>:UD vme_wb1.0<8,8,1>:UD {align1};
+mov (8) msg_reg2.0<1>:ud vme_wb2.0<8,8,1>:ud {align1};
+mov (8) msg_reg3.0<1>:ud vme_wb3.0<8,8,1>:ud {align1};
+mov (8) msg_reg4.0<1>:ud vme_wb4.0<8,8,1>:ud {align1};
+/* bind index 3, write 8 oword (128 bytes), msg type: 8(OWord Block Write) */
+send (16)
+ msg_ind
+ obw_wb
+ null
+ data_port(
+ OBW_CACHE_TYPE,
+ OBW_MESSAGE_TYPE,
+ OBW_CONTROL_8,
+ OBW_BIND_IDX,
+ OBW_WRITE_COMMIT_CATEGORY,
+ OBW_HEADER_PRESENT
+ )
+ mlen 5
+ rlen obw_wb_length
+ {align1};
+
+/* Write IME RefID */
+add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x08:UD {align1};
+mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1};
+
+mov (8) msg_reg1.0<1>:UD vme_wb6.0<8,8,1>:UD {align1};
+
+/* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */
+send (16)
+ msg_ind
+ obw_wb
+ null
+ data_port(
+ OBW_CACHE_TYPE,
+ OBW_MESSAGE_TYPE,
+ OBW_CONTROL_2,
+ OBW_BIND_IDX,
+ OBW_WRITE_COMMIT_CATEGORY,
+ OBW_HEADER_PRESENT
+ )
+ mlen 2
+ rlen obw_wb_length
+ {align1};
+
+/* Send FBR message into CRE */
+
+mov (8) vme_msg_3.0<1>:UD vme_wb1.0<8,8,1>:UD {align1};
+mov (8) vme_msg_4.0<1>:ud vme_wb2.0<8,8,1>:ud {align1};
+mov (8) vme_msg_5.0<1>:ud vme_wb3.0<8,8,1>:ud {align1};
+mov (8) vme_msg_6.0<1>:ud vme_wb4.0<8,8,1>:ud {align1};
+
+mov (1) vme_m0.12<1>:UD INTER_SAD_HAAR + SUB_PEL_MODE_QUARTER + FBR_BME_DISABLE:UD {align1}; /* 16x16 Source, 1/4 pixel, harr, BME disable */
+mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1};
+mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1};
+
+mov (8) vme_msg_2.0<1>:UD vme_m2.0<8,8,1>:UD {align1};
+
+/* after verification it will be passed by using payload */
+send (8)
+ vme_msg_ind
+ vme_wb<1>:UD
+ null
+ cre(
+ BIND_IDX_VME,
+ VME_FBR_MESSAGE_TYPE
+ )
+ mlen fbr_vme_msg_length
+ rlen vme_wb_length
+ {align1};
+
+add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x02:UD {align1};
+mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1};
+/* write FME info */
+mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1};
+
+mov (1) msg_reg1.4<1>:UD vme_wb.24<0,1,0>:UD {align1};
+/* Inter distortion of FME */
+mov (1) msg_reg1.8<1>:UD vme_wb.8<0,1,0>:UD {align1};
+
+mov (1) msg_reg1.12<1>:UD vme_m2.20<0,1,0>:UD {align1};
+
+/* bind index 3, write oword (16bytes), msg type: 8(OWord Block Write) */
+send (16)
+ msg_ind
+ obw_wb
+ null
+ data_port(
+ OBW_CACHE_TYPE,
+ OBW_MESSAGE_TYPE,
+ OBW_CONTROL_0,
+ OBW_BIND_IDX,
+ OBW_WRITE_COMMIT_CATEGORY,
+ OBW_HEADER_PRESENT
+ )
+ mlen 2
+ rlen obw_wb_length
+ {align1};
+
+/* Write FME/BME MV */
+add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x01:UD {align1};
+mov (8) msg_reg0.0<1>:UD obw_m0.0<8,8,1>:UD {align1};
+
+
+mov (8) msg_reg1.0<1>:UD vme_wb1.0<8,8,1>:UD {align1};
+mov (8) msg_reg2.0<1>:ud vme_wb2.0<8,8,1>:ud {align1};
+mov (8) msg_reg3.0<1>:ud vme_wb3.0<8,8,1>:ud {align1};
+mov (8) msg_reg4.0<1>:ud vme_wb4.0<8,8,1>:ud {align1};
+/* bind index 3, write 8 oword (128 bytes), msg type: 8(OWord Block Write) */
+send (16)
+ msg_ind
+ obw_wb
+ null
+ data_port(
+ OBW_CACHE_TYPE,
+ OBW_MESSAGE_TYPE,
+ OBW_CONTROL_8,
+ OBW_BIND_IDX,
+ OBW_WRITE_COMMIT_CATEGORY,
+ OBW_HEADER_PRESENT
+ )
+ mlen 5
+ rlen obw_wb_length
+ {align1};
+
+/* Write FME/BME RefID */
+add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x08:UD {align1};
+mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1};
+
+mov (8) msg_reg1.0<1>:UD vme_wb6.0<8,8,1>:UD {align1};
+
+/* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */
+send (16)
+ msg_ind
+ obw_wb
+ null
+ data_port(
+ OBW_CACHE_TYPE,
+ OBW_MESSAGE_TYPE,
+ OBW_CONTROL_2,
+ OBW_BIND_IDX,
+ OBW_WRITE_COMMIT_CATEGORY,
+ OBW_HEADER_PRESENT
+ )
+ mlen 2
+ rlen obw_wb_length
+ {align1};
+
+__EXIT:
+/*
+ * kill thread
+ */
+mov (8) ts_msg_reg0<1>:UD r0<8,8,1>:UD {align1};
+send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
--- /dev/null
+#include "vme75.inc"
+#include "inter_frame_haswell.asm"
--- /dev/null
+ { 0x00800001, 0x24000061, 0x00000000, 0x00000000 },
+ { 0x00800001, 0x24400061, 0x00000000, 0x00000000 },
+ { 0x00800001, 0x24800061, 0x00000000, 0x00000000 },
+ { 0x00800001, 0x24c00061, 0x00000000, 0x00000000 },
+ { 0x00200009, 0x24002e25, 0x004500a0, 0x00040004 },
+ { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 },
+ { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff },
+ { 0x00000001, 0x240800e1, 0x00000000, 0x0000001f },
+ { 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
+ { 0x00200009, 0x24202e25, 0x004500a0, 0x00040004 },
+ { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc },
+ { 0x00000001, 0x242800e1, 0x00000000, 0x000f0003 },
+ { 0x00000001, 0x24340231, 0x00000014, 0x00000000 },
+ { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 },
+ { 0x00000001, 0x24540231, 0x00000014, 0x00000000 },
+ { 0x00000041, 0x24884521, 0x000000a2, 0x000000a1 },
+ { 0x00000040, 0x24884421, 0x00000488, 0x000000a0 },
+ { 0x00000041, 0x24880c21, 0x00000488, 0x00000018 },
+ { 0x00000001, 0x24940231, 0x00000014, 0x00000000 },
+ { 0x00600001, 0x28000021, 0x008d0400, 0x00000000 },
+ { 0x04600031, 0x23801cb1, 0x00000800, 0x02190004 },
+ { 0x00600001, 0x28000021, 0x008d0420, 0x00000000 },
+ { 0x04600031, 0x23a01cb1, 0x00000800, 0x02290004 },
+ { 0x00200009, 0x24002e25, 0x004500a0, 0x00030003 },
+ { 0x00000041, 0x24003ca5, 0x00000400, 0x00020002 },
+ { 0x00000040, 0x24003ca5, 0x00000400, 0xfff8fff8 },
+ { 0x00000040, 0x24043ca5, 0x00000404, 0xffffffff },
+ { 0x00600001, 0x28000021, 0x008d0400, 0x00000000 },
+ { 0x04600031, 0x26001cb1, 0x00000800, 0x02190006 },
+ { 0x00200009, 0x24202e25, 0x004500a0, 0x00030003 },
+ { 0x00000041, 0x24203ca5, 0x00000420, 0x00020002 },
+ { 0x00000040, 0x24203ca5, 0x00000420, 0xfffcfffc },
+ { 0x00000001, 0x242800e1, 0x00000000, 0x00070003 },
+ { 0x00600001, 0x28000021, 0x008d0420, 0x00000000 },
+ { 0x04600031, 0x26201cb1, 0x00000800, 0x02190006 },
+ { 0x00600001, 0x25600021, 0x008d0020, 0x00000000 },
+ { 0x00600001, 0x28400021, 0x008d0560, 0x00000000 },
+ { 0x00600001, 0x28600061, 0x00000000, 0x00000000 },
+ { 0x00000001, 0x23800061, 0x00000000, 0x00000000 },
+ { 0x00000005, 0x23840c21, 0x00000384, 0xff000000 },
+ { 0x00600001, 0x28800021, 0x008d0380, 0x00000000 },
+ { 0x00600001, 0x28a00061, 0x00000000, 0x00000000 },
+ { 0x00800001, 0x28a00231, 0x00cf03a3, 0x00000000 },
+ { 0x00000001, 0x28b00061, 0x00000000, 0x11111111 },
+ { 0x00000001, 0x28bc0061, 0x00000000, 0x00010101 },
+ { 0x00000001, 0x28b40129, 0x00000606, 0x00000000 },
+ { 0x00400001, 0x28d00021, 0x00690608, 0x00000000 },
+ { 0x00600001, 0x28c00129, 0x00ae0622, 0x00000000 },
+ { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 },
+ { 0x00000001, 0x24000169, 0x00000000, 0x00010001 },
+ { 0x00000001, 0x28850231, 0x00000400, 0x00000000 },
+ { 0x00000001, 0x247c0169, 0x00000000, 0x00000000 },
+ { 0x01000005, 0x20002e28, 0x000000a4, 0x00010001 },
+ { 0x00010001, 0x247c00f1, 0x00000000, 0x00000002 },
+ { 0x02000010, 0x20002e28, 0x000000a0, 0x00000000 },
+ { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000060 },
+ { 0x02000010, 0x20002e28, 0x000000a1, 0x00000000 },
+ { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000010 },
+ { 0x02000041, 0x20004628, 0x000000a0, 0x000000a1 },
+ { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000004 },
+ { 0x00000040, 0x25202e2d, 0x000000a0, 0x00010001 },
+ { 0x00000040, 0x2520352d, 0x000000a2, 0x00004520 },
+ { 0x02000041, 0x200045a0, 0x00000520, 0x000000a1 },
+ { 0x00010040, 0x247d1e31, 0x0000047d, 0x00000008 },
+ { 0x02000005, 0x20002e28, 0x000000a4, 0x00020002 },
+ { 0x00010005, 0x247d1e31, 0x0000047d, 0x000000e0 },
+ { 0x00000001, 0x24000169, 0x00000000, 0x00200020 },
+ { 0x00000001, 0x247e0231, 0x00000400, 0x00000000 },
+ { 0x00000001, 0x244c0061, 0x00000000, 0x00800000 },
+ { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 },
+ { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 },
+ { 0x0d600031, 0x21801ca1, 0x00000800, 0x0e782000 },
+ { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 },
+ { 0x00000001, 0x28200021, 0x00000180, 0x00000000 },
+ { 0x00000001, 0x28240021, 0x00000190, 0x00000000 },
+ { 0x00000001, 0x28280021, 0x00000194, 0x00000000 },
+ { 0x00000001, 0x282c0021, 0x00000198, 0x00000000 },
+ { 0x00000001, 0x28300129, 0x0000018c, 0x00000000 },
+ { 0x00000001, 0x28340021, 0x00000188, 0x00000000 },
+ { 0x00000001, 0x28380021, 0x0000019c, 0x00000000 },
+ { 0x00000001, 0x283c0021, 0x00000488, 0x00000000 },
+ { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0203 },
+ { 0x00000001, 0x244c0061, 0x00000000, 0x00200000 },
+ { 0x00000001, 0x24560169, 0x00000000, 0x28302830 },
+ { 0x00000001, 0x24400021, 0x00000448, 0x00000000 },
+ { 0x00000040, 0x24403dad, 0x00000440, 0xfff0fff0 },
+ { 0x00000040, 0x24423dad, 0x00000442, 0xfff4fff4 },
+ { 0x00000001, 0x244001ed, 0x00000000, 0xfff0fff0 },
+ { 0x00000001, 0x244201ed, 0x00000000, 0xfff4fff4 },
+ { 0x00000001, 0x24440021, 0x00000440, 0x00000000 },
+ { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 },
+ { 0x00000001, 0x24600061, 0x00000000, 0x00000002 },
+ { 0x00000001, 0x24640061, 0x00000000, 0x00000020 },
+ { 0x00000001, 0x24680061, 0x00000000, 0x30003030 },
+ { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 },
+ { 0x00600001, 0x28400021, 0x008d0560, 0x00000000 },
+ { 0x00000001, 0x28600061, 0x00000000, 0x01010101 },
+ { 0x00000001, 0x28640061, 0x00000000, 0x10010101 },
+ { 0x00000001, 0x28680061, 0x00000000, 0x0f0f0f0f },
+ { 0x00000001, 0x286c0061, 0x00000000, 0x100f0f0f },
+ { 0x00000001, 0x28700061, 0x00000000, 0x01010101 },
+ { 0x00000001, 0x28740061, 0x00000000, 0x10010101 },
+ { 0x00000001, 0x28780061, 0x00000000, 0x0f0f0f0f },
+ { 0x00000001, 0x287c0061, 0x00000000, 0x100f0f0f },
+ { 0x00000001, 0x28800061, 0x00000000, 0x01010101 },
+ { 0x00000001, 0x28840061, 0x00000000, 0x10010101 },
+ { 0x00000001, 0x28880061, 0x00000000, 0x0f0f0f0f },
+ { 0x00000001, 0x288c0061, 0x00000000, 0x000f0f0f },
+ { 0x00400001, 0x28900061, 0x00000000, 0x00000000 },
+ { 0x08600031, 0x21801ca1, 0x00000800, 0x0a784000 },
+ { 0x00000001, 0x25740061, 0x00000000, 0x00000000 },
+ { 0x00000001, 0x25750231, 0x00000199, 0x00000000 },
+ { 0x00000001, 0x25760231, 0x0000019a, 0x00000000 },
+ { 0x00000005, 0x24002d29, 0x00000180, 0x00030003 },
+ { 0x00000001, 0x25740231, 0x00000400, 0x00000000 },
+ { 0x00000040, 0x24880c21, 0x00000488, 0x00000002 },
+ { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 },
+ { 0x00000001, 0x28200021, 0x00000180, 0x00000000 },
+ { 0x00000001, 0x28240021, 0x00000198, 0x00000000 },
+ { 0x00000001, 0x28280021, 0x00000188, 0x00000000 },
+ { 0x00000001, 0x282c0021, 0x00000488, 0x00000000 },
+ { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0003 },
+ { 0x00000040, 0x24880c21, 0x00000488, 0x00000001 },
+ { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 },
+ { 0x00600001, 0x28200021, 0x008d01a0, 0x00000000 },
+ { 0x00600001, 0x28400021, 0x008d01c0, 0x00000000 },
+ { 0x00600001, 0x28600021, 0x008d01e0, 0x00000000 },
+ { 0x00600001, 0x28800021, 0x008d0200, 0x00000000 },
+ { 0x0a800031, 0x20001cac, 0x00000800, 0x0a0a0403 },
+ { 0x00000040, 0x24880c21, 0x00000488, 0x00000008 },
+ { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 },
+ { 0x00600001, 0x28200021, 0x008d0240, 0x00000000 },
+ { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0203 },
+ { 0x00600001, 0x28600021, 0x008d01a0, 0x00000000 },
+ { 0x00600001, 0x28800021, 0x008d01c0, 0x00000000 },
+ { 0x00600001, 0x28a00021, 0x008d01e0, 0x00000000 },
+ { 0x00600001, 0x28c00021, 0x008d0200, 0x00000000 },
+ { 0x00000001, 0x244c0061, 0x00000000, 0x00243000 },
+ { 0x00600001, 0x28000021, 0x008d0440, 0x00000000 },
+ { 0x00600001, 0x28200021, 0x008d0460, 0x00000000 },
+ { 0x00600001, 0x28400021, 0x008d0560, 0x00000000 },
+ { 0x0d600031, 0x21801ca1, 0x00000800, 0x0e786000 },
+ { 0x00000040, 0x24880c21, 0x00000488, 0x00000002 },
+ { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 },
+ { 0x00000001, 0x28200021, 0x00000180, 0x00000000 },
+ { 0x00000001, 0x28240021, 0x00000198, 0x00000000 },
+ { 0x00000001, 0x28280021, 0x00000188, 0x00000000 },
+ { 0x00000001, 0x282c0021, 0x00000574, 0x00000000 },
+ { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0003 },
+ { 0x00000040, 0x24880c21, 0x00000488, 0x00000001 },
+ { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 },
+ { 0x00600001, 0x28200021, 0x008d01a0, 0x00000000 },
+ { 0x00600001, 0x28400021, 0x008d01c0, 0x00000000 },
+ { 0x00600001, 0x28600021, 0x008d01e0, 0x00000000 },
+ { 0x00600001, 0x28800021, 0x008d0200, 0x00000000 },
+ { 0x0a800031, 0x20001cac, 0x00000800, 0x0a0a0403 },
+ { 0x00000040, 0x24880c21, 0x00000488, 0x00000008 },
+ { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 },
+ { 0x00600001, 0x28200021, 0x008d0240, 0x00000000 },
+ { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0203 },
+ { 0x00600001, 0x2e000021, 0x008d0000, 0x00000000 },
+ { 0x07800031, 0x24001ca8, 0x00000e00, 0x82000010 },
define(`OBW_CONTROL_1', `1') /* 1 OWord, high 128 bits */
define(`OBW_CONTROL_2', `2') /* 2 OWords */
define(`OBW_CONTROL_3', `3') /* 4 OWords */
-define(`OBW_CONTROL_4', `4') /* 8 OWords */
+define(`OBW_CONTROL_8', `4') /* 8 OWords */
+define(`FBR_BME_ENABLE', `0x00000000')
+define(`FBR_BME_DISABLE', `0x00040000')
define(`OBW_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */
define(`tmp_uw6', `tmp_rega.12')
define(`tmp_uw7', `tmp_rega.14')
+define(`vme_m2', `r43')
/*
* MRF registers
*/
define(`vme_wb_length', `7')
define(`sic_vme_msg_length', `7')
define(`fbr_vme_msg_length', `7')
-define(`ime_vme_msg_length', `10')
+define(`ime_vme_msg_length', `5')
define(`vme_msg_ind', `msg_ind')
define(`vme_msg_0', `msg_reg0')
projects / profile / ivi / vaapi-intel-driver.git / commitdiff