clk: imx: Correct the root clk of media ldb on imx8mp
authorJacky Bai <ping.bai@nxp.com>
Mon, 24 Aug 2020 07:37:01 +0000 (15:37 +0800)
committerShawn Guo <shawnguo@kernel.org>
Mon, 31 Aug 2020 02:26:57 +0000 (10:26 +0800)
The root clock slice at 0xbf00 is media_ldb clock,
not csi_phy2_ref, so correct it.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
drivers/clk/imx/clk-imx8mp.c
include/dt-bindings/clock/imx8mp-clock.h

index f3cedf2..4a8fbe2 100644 (file)
@@ -375,10 +375,10 @@ static const char * const imx8mp_media_cam2_pix_sels[] = {"osc_24m", "sys_pll1_2
                                                          "sys_pll3_out", "audio_pll2_out",
                                                          "video_pll1_out", };
 
-static const char * const imx8mp_media_mipi_phy2_ref_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
-                                                              "sys_pll1_800m", "sys_pll2_1000m",
-                                                              "clk_ext2", "audio_pll2_out",
-                                                              "video_pll1_out", };
+static const char * const imx8mp_media_ldb_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
+                                                    "sys_pll1_800m", "sys_pll2_1000m",
+                                                    "clk_ext2", "audio_pll2_out",
+                                                    "video_pll1_out", };
 
 static const char * const imx8mp_media_mipi_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m",
                                                               "sys_pll1_800m", "sys_pll2_1000m",
@@ -647,7 +647,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
        hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] = imx8m_clk_hw_composite("media_mipi_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, ccm_base + 0xbd80);
        hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite("media_disp1_pix", imx8mp_media_disp1_pix_sels, ccm_base + 0xbe00);
        hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base + 0xbe80);
-       hws[IMX8MP_CLK_MEDIA_MIPI_PHY2_REF] = imx8m_clk_hw_composite("media_mipi_phy2_ref", imx8mp_media_mipi_phy2_ref_sels, ccm_base + 0xbf00);
+       hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb", imx8mp_media_ldb_sels, ccm_base + 0xbf00);
        hws[IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC] = imx8m_clk_hw_composite("media_mipi_csi2_esc", imx8mp_media_mipi_csi2_esc_sels, ccm_base + 0xbf80);
        hws[IMX8MP_CLK_PCIE2_CTRL] = imx8m_clk_hw_composite("pcie2_ctrl", imx8mp_pcie2_ctrl_sels, ccm_base + 0xc000);
        hws[IMX8MP_CLK_PCIE2_PHY] = imx8m_clk_hw_composite("pcie2_phy", imx8mp_pcie2_phy_sels, ccm_base + 0xc080);
index 7a23f28..e8d68fb 100644 (file)
 #define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF         171
 #define IMX8MP_CLK_MEDIA_DISP1_PIX             172
 #define IMX8MP_CLK_MEDIA_CAM2_PIX              173
-#define IMX8MP_CLK_MEDIA_MIPI_PHY2_REF         174
+#define IMX8MP_CLK_MEDIA_LDB                   174
 #define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC         175
 #define IMX8MP_CLK_PCIE2_CTRL                  176
 #define IMX8MP_CLK_PCIE2_PHY                   177