#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
#define PCI_CHIP_HASWELL_GT2 0x0412
-#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422
+#define PCI_CHIP_HASWELL_GT3 0x0422
#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
#define PCI_CHIP_HASWELL_M_GT2 0x0416
-#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
+#define PCI_CHIP_HASWELL_M_GT3 0x0426
#define PCI_CHIP_HASWELL_S_GT1 0x040a /* Server */
#define PCI_CHIP_HASWELL_S_GT2 0x041a
-#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042a
+#define PCI_CHIP_HASWELL_S_GT3 0x042a
#define PCI_CHIP_HASWELL_SDV_GT1 0x0c02 /* Desktop */
#define PCI_CHIP_HASWELL_SDV_GT2 0x0c12
-#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0c22
+#define PCI_CHIP_HASWELL_SDV_GT3 0x0c22
#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0c06 /* Mobile */
#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0c16
-#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0c26
+#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0c26
#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0c0a /* Server */
#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0c1a
-#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0c2a
+#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0c2a
#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
-#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22
+#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
-#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
+#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
-#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
+#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
-#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22
+#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26
+#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A
+#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
#define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \
devid == PCI_CHIP_Q45_G || \
devid == PCI_CHIP_HASWELL_CRW_M_GT2|| \
devid == PCI_CHIP_HASWELL_CRW_S_GT2|| \
devid == PCI_CHIP_HASWELL_ULT_GT2|| \
- devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS|| \
devid == PCI_CHIP_HASWELL_ULT_M_GT2|| \
- devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS|| \
- devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
- devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_GT2_PLUS|| \
- devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS|| \
- devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS|| \
- devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS|| \
- devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS|| \
- devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS|| \
- devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
+ devid == PCI_CHIP_HASWELL_ULT_S_GT2)
+
+#define IS_HSW_GT3(devid) (devid == PCI_CHIP_HASWELL_GT3 || \
+ devid == PCI_CHIP_HASWELL_M_GT3 || \
+ devid == PCI_CHIP_HASWELL_S_GT3 || \
+ devid == PCI_CHIP_HASWELL_SDV_GT3 || \
+ devid == PCI_CHIP_HASWELL_SDV_M_GT3 || \
+ devid == PCI_CHIP_HASWELL_SDV_S_GT3 || \
+ devid == PCI_CHIP_HASWELL_CRW_GT3 || \
+ devid == PCI_CHIP_HASWELL_CRW_M_GT3 || \
+ devid == PCI_CHIP_HASWELL_CRW_S_GT3 || \
+ devid == PCI_CHIP_HASWELL_ULT_GT3 || \
+ devid == PCI_CHIP_HASWELL_ULT_M_GT3 || \
+ devid == PCI_CHIP_HASWELL_ULT_S_GT3)
#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
- IS_HSW_GT2(devid))
+ IS_HSW_GT2(devid) || \
+ IS_HSW_GT3(devid))
#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
IS_HASWELL(devid))