clk: samsung: add 933MHz clock to bpll

Change-Id: I9951d067e530e6bd9393cfe1fc7789be7ed06488
Signed-off-by: Inki Dae <inki.dae@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 3e691377dc4598aa7c72da0c9b46a62466913a1a..caf98b4b0a8c0292b9dfb63d8dd7dcbb5300dc11 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1275,6 +1275,7 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini
        PLL_35XX_RATE(1200000000, 200, 2, 1),
        PLL_35XX_RATE(1100000000, 275, 3, 1),
        PLL_35XX_RATE(1000000000, 250, 3, 1),
+       PLL_35XX_RATE(933000000,  233, 3, 1),
        PLL_35XX_RATE(900000000,  150, 2, 1),
        PLL_35XX_RATE(800000000,  200, 3, 1),
        PLL_35XX_RATE(700000000,  175, 3, 1),