radv: Really use correct HTILE expanded words.
authorJames Legg <jlegg@feralinteractive.com>
Thu, 22 Feb 2018 16:57:53 +0000 (16:57 +0000)
committerBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Sat, 24 Feb 2018 01:16:22 +0000 (02:16 +0100)
When transitioning to an htile compressed depth format, Set the full
depth range, so later rasterization can pass HiZ. Previously, for depth
only formats, the depth range was set to 0 to 0. This caused unwanted
HiZ rejections with a VK_FORMAT_D16_UNORM depth buffer
(VK_FORMAT_D32_SFLOAT was not affected somehow).

These values are derived from PAL [0], since I can't find the
specification describing the htile values.

[0] https://github.com/GPUOpen-Drivers/pal/blob/5cba4ecbda9452773f59692f5915301e7db4a183/src/core/hw/gfxip/gfx9/gfx9MaskRam.cpp#L1500

CC: Dave Airlie <airlied@redhat.com>
CC: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Fixes: 5158603182fe7435 "radv: Use correct HTILE expanded words."

src/amd/vulkan/radv_cmd_buffer.c

index 8a384b1..2b41bae 100644 (file)
@@ -3440,8 +3440,8 @@ void radv_CmdEndRenderPass(
 
 /*
  * For HTILE we have the following interesting clear words:
- *   0x0000030f: Uncompressed for depth+stencil HTILE.
- *   0x0000000f: Uncompressed for depth only HTILE.
+ *   0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
+ *   0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
  *   0xfffffff0: Clear depth to 1.0
  *   0x00000000: Clear depth to 0.0
  */
@@ -3489,7 +3489,7 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe
                radv_initialize_htile(cmd_buffer, image, range, 0);
        } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
                   radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
-               uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0x30f : 0xf;
+               uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
                radv_initialize_htile(cmd_buffer, image, range, clear_value);
        } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
                   !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {