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ASoC: fsl_micfil: explicitly clear software reset bit
author
Shengjiu Wang
<shengjiu.wang@nxp.com>
Sat, 7 May 2022 12:14:13 +0000
(20:14 +0800)
committer
Greg Kroah-Hartman
<gregkh@linuxfoundation.org>
Mon, 19 Dec 2022 11:36:40 +0000
(12:36 +0100)
[ Upstream commit
292709b9cf3ba470af94b62c9bb60284cc581b79
]
SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined as
non volatile register, it still remain in regmap cache after set,
then every update of REG_MICFIL_CTRL1, software reset happens.
to avoid this, clear it explicitly.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link:
https://lore.kernel.org/r/1651925654-32060-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
sound/soc/fsl/fsl_micfil.c
patch
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diff --git
a/sound/soc/fsl/fsl_micfil.c
b/sound/soc/fsl/fsl_micfil.c
index
9f90989
..
cb84d95
100644
(file)
--- a/
sound/soc/fsl/fsl_micfil.c
+++ b/
sound/soc/fsl/fsl_micfil.c
@@
-191,6
+191,17
@@
static int fsl_micfil_reset(struct device *dev)
return ret;
}
+ /*
+ * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined
+ * as non-volatile register, so SRES still remain in regmap
+ * cache after set, that every update of REG_MICFIL_CTRL1,
+ * software reset happens. so clear it explicitly.
+ */
+ ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
+ MICFIL_CTRL1_SRES);
+ if (ret)
+ return ret;
+
return 0;
}