The regex was looking for JECXZ_32 or JECXZ_64, but their is just one instruction called JECXZ. They used to exist as separate instructions, but were merged over 3 years ago.
llvm-svn: 327880
// J(E|R)CXZ.
def ZnWriteJCXZ : SchedWriteRes<[ZnALU03]>;
-def : InstRW<[ZnWriteJCXZ], (instregex "JCXZ", "JECXZ_(32|64)", "JRCXZ")>;
+def : InstRW<[ZnWriteJCXZ], (instrs JCXZ, JECXZ, JRCXZ)>;
// INTO
def : InstRW<[WriteMicrocoded], (instregex "INTO")>;
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: JXTGT:
; ZNVER1-NEXT: jcxz JXTGT # sched: [1:0.50]
-; ZNVER1-NEXT: jecxz JXTGT # sched: [1:0.25]
+; ZNVER1-NEXT: jecxz JXTGT # sched: [1:0.50]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
call void asm sideeffect "JXTGT: \0A\09 jcxz JXTGT \0A\09 jecxz JXTGT", ""()
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: JXTGT:
-; ZNVER1-NEXT: jecxz JXTGT # sched: [1:0.25]
+; ZNVER1-NEXT: jecxz JXTGT # sched: [1:0.50]
; ZNVER1-NEXT: jrcxz JXTGT # sched: [1:0.50]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retq # sched: [1:0.50]