{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
struct i915_power_well *well;
+ u32 val;
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
if (resume && dev_priv->csr.dmc_payload)
intel_csr_load_program(dev_priv);
+
+ /* Wa_14011508470 */
+ if (IS_GEN(dev_priv, 12)) {
+ val = DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM |
+ DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR;
+ intel_uncore_rmw(&dev_priv->uncore, GEN11_CHICKEN_DCPR_2, 0, val);
+ }
}
static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
#define MASK_WAKEMEM (1 << 13)
#define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
+#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
+#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
+#define DCPR_MASK_LPMODE REG_BIT(26)
+#define DCPR_SEND_RESP_IMM REG_BIT(25)
+#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
+
#define SKL_DFSM _MMIO(0x51000)
#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)