dt-bindings: clock: renesas: r9a06g032-sysctrl: Document power Domains

The driver is gaining power domain support, so add the new property
to the DT binding and update the examples.

Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt
index d60b997..aed713c 100644 (file)
--- a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt
@@ -13,6 +13,7 @@ Required Properties:
        - external (optional) RGMII_REFCLK
   - clock-names: Must be:
         clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+  - #power-domain-cells: Must be 0
 
 Examples
 --------
@@ -27,6 +28,7 @@ Examples
                clocks = <&ext_mclk>, <&ext_rtc_clk>,
                                <&ext_jtag_clk>, <&ext_rgmii_ref>;
                clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+               #power-domain-cells = <0>;
        };
 
   - Other nodes can use the clocks provided by SYSCTRL as in:
@@ -38,6 +40,7 @@ Examples
                interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
-               clocks = <&sysctrl R9A06G032_CLK_UART0>;
-               clock-names = "baudclk";
+               clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
+               clock-names = "baudclk", "apb_pclk";
+               power-domains = <&sysctrl>;
        };