out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
-#ifdef CONFIG_FSL_DCU_FB
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
#endif
#ifndef __ASSEMBLY__
+#include <linux/types.h>
+
/* Clock Controller Module (CCM) */
struct ccm_reg {
u32 ccr;
#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7)
+#define CCM_CSCMR1_DCU1_CLK_SEL (1 << 29)
+#define CCM_CSCMR1_DCU0_CLK_SEL (1 << 28)
+
#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET 22
#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22)
#define CCM_CSCMR1_QSPI0_CLK_SEL(v) (((v) & 0x3) << 22)
#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
+#define CCM_CSCDR3_DCU1_EN (1 << 23)
+#define CCM_CSCDR3_DCU1_DIV_MASK (0x7 << 20)
+#define CCM_CSCDR3_DCU1_DIV(v) (((v) & 0x7) << 20)
+#define CCM_CSCDR3_DCU0_EN (1 << 19)
+#define CCM_CSCDR3_DCU0_DIV_MASK (0x7 << 16)
+#define CCM_CSCDR3_DCU0_DIV(v) (((v) & 0x7) << 16)
+
#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13
#define CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13)
#define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13)
#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26)
#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)
#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
+#define CCM_CCGR1_TCON0_CTRL_MASK (0x3 << 26)
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8)
#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16)
#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26)
#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
#define CCM_CCGR3_SCSC_CTRL_MASK (0x3 << 4)
+#define CCM_CCGR3_DCU0_CTRL_MASK (0x3 << 16)
#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22)
#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
#define USB_PHY0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050800)
#define USB_PHY1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050C00)
#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
+#define DCU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00058000)
#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000)
#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000)
#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
#define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000)
#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
#define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000)
+#define DCU1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00058000)
#define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x00060000)
#define QSPI0_AMBA_BASE 0x20000000
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
#define VF610_DSPI_SIN_PAD_CTRL (PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
+#define VF610_DCU_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
+ PAD_CTL_DSE_37ohm | PAD_CTL_OBE_ENABLE)
enum {
VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+ VF610_PAD_PTE0__DCU0_HSYNC = IOMUX_PAD(0x01a4, 0x01a4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE1__DCU0_VSYNC = IOMUX_PAD(0x01a8, 0x01a8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE2__DCU0_PCLK = IOMUX_PAD(0x01ac, 0x01ac, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE4__DCU0_DE = IOMUX_PAD(0x01b4, 0x01b4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE5__DCU0_R0 = IOMUX_PAD(0x01b8, 0x01b8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE6__DCU0_R1 = IOMUX_PAD(0x01bc, 0x01bc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE7__DCU0_R2 = IOMUX_PAD(0x01c0, 0x01c0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE8__DCU0_R3 = IOMUX_PAD(0x01c4, 0x01c4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE9__DCU0_R4 = IOMUX_PAD(0x01c8, 0x01c8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE10__DCU0_R5 = IOMUX_PAD(0x01cc, 0x01cc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE11__DCU0_R6 = IOMUX_PAD(0x01d0, 0x01d0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE12__DCU0_R7 = IOMUX_PAD(0x01d4, 0x01d4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE13__DCU0_G0 = IOMUX_PAD(0x01d8, 0x01d8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE14__DCU0_G1 = IOMUX_PAD(0x01dc, 0x01dc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE15__DCU0_G2 = IOMUX_PAD(0x01e0, 0x01e0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE16__DCU0_G3 = IOMUX_PAD(0x01e4, 0x01e4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE17__DCU0_G4 = IOMUX_PAD(0x01e8, 0x01e8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE18__DCU0_G5 = IOMUX_PAD(0x01ec, 0x01ec, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE19__DCU0_G6 = IOMUX_PAD(0x01f0, 0x01f0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE20__DCU0_G7 = IOMUX_PAD(0x01f4, 0x01f4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE21__DCU0_B0 = IOMUX_PAD(0x01f8, 0x01f8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE22__DCU0_B1 = IOMUX_PAD(0x01fc, 0x01fc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE23__DCU0_B2 = IOMUX_PAD(0x0200, 0x0200, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE24__DCU0_B3 = IOMUX_PAD(0x0204, 0x0204, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE25__DCU0_B4 = IOMUX_PAD(0x0208, 0x0208, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE26__DCU0_B5 = IOMUX_PAD(0x020c, 0x020c, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE27__DCU0_B6 = IOMUX_PAD(0x0210, 0x0210, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE28__DCU0_B7 = IOMUX_PAD(0x0214, 0x0214, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+
VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
#define PAD_CTL_ODE (1 << 10)
#define PAD_CTL_DSE_150ohm (1 << 6)
+#define PAD_CTL_DSE_75ohm (2 << 6)
#define PAD_CTL_DSE_50ohm (3 << 6)
+#define PAD_CTL_DSE_37ohm (4 << 6)
+#define PAD_CTL_DSE_30ohm (5 << 6)
#define PAD_CTL_DSE_25ohm (6 << 6)
#define PAD_CTL_DSE_20ohm (7 << 6)
endif
ifneq ($(CONFIG_OMAP54XX),)
+ifeq ($(CONFIG_DM_SCSI),)
obj-y += pipe3-phy.o
obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
endif
+endif
ifeq ($(CONFIG_SYS_DCACHE_OFF),)
obj-y += omap-cache.o
(*prcm)->cm_l4per_gpio6_clkctrl,
(*prcm)->cm_l4per_gpio7_clkctrl,
(*prcm)->cm_l4per_gpio8_clkctrl,
+#ifdef CONFIG_SCSI_AHCI_PLAT
+ (*prcm)->cm_l3init_ocp2scp3_clkctrl,
+#endif
0
};
#ifdef CONFIG_TI_QSPI
(*prcm)->cm_l4per_qspi_clkctrl,
#endif
+#ifdef CONFIG_SCSI_AHCI_PLAT
+ (*prcm)->cm_l3init_sata_clkctrl,
+#endif
0
};
setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
#endif
+#ifdef CONFIG_SCSI_AHCI_PLAT
+ /* Enable optional functional clock for SATA */
+ setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
+ SATA_CLKCTRL_OPTFCLKEN_MASK);
+#endif
+
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
int ret;
u32 val;
- u32 const clk_domains_sata[] = {
- 0
- };
-
- u32 const clk_modules_hw_auto_sata[] = {
- (*prcm)->cm_l3init_ocp2scp3_clkctrl,
- 0
- };
-
- u32 const clk_modules_explicit_en_sata[] = {
- (*prcm)->cm_l3init_sata_clkctrl,
- 0
- };
-
- do_enable_clocks(clk_domains_sata,
- clk_modules_hw_auto_sata,
- clk_modules_explicit_en_sata,
- 0);
-
- /* Enable optional functional clock for SATA */
- setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
- SATA_CLKCTRL_OPTFCLKEN_MASK);
-
sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
/* Power up the PHY */
yres = <768>;
};
+ leds {
+ compatible = "gpio-leds";
+
+ iracibble {
+ gpios = <&gpio_a 1 0>;
+ label = "sandbox:red";
+ };
+
+ martinet {
+ gpios = <&gpio_a 2 0>;
+ label = "sandbox:green";
+ };
+ };
+
pci: pci-controller {
compatible = "sandbox,pci";
device_type = "pci";
*/
#include <common.h>
-#include <mmc.h>
#include <asm/io.h>
#include <asm/arch/sama5d3_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
-#include <atmel_mci.h>
-#include <net.h>
-#include <netdev.h>
+#include <debug_uart.h>
#include <spl.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/at91_wdt.h>
#ifdef CONFIG_GENERIC_ATMEL_MCI
static void sama5d3_xplained_mci0_hw_init(void)
{
- at91_mci_hw_init();
-
at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */
}
#endif
-int board_early_init_f(void)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
{
- at91_periph_clk_enable(ATMEL_ID_PIOA);
- at91_periph_clk_enable(ATMEL_ID_PIOB);
- at91_periph_clk_enable(ATMEL_ID_PIOC);
- at91_periph_clk_enable(ATMEL_ID_PIOD);
- at91_periph_clk_enable(ATMEL_ID_PIOE);
-
at91_seriald_hw_init();
+}
+#endif
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
return 0;
}
+#endif
int board_init(void)
{
#ifdef CONFIG_GENERIC_ATMEL_MCI
sama5d3_xplained_mci0_hw_init();
#endif
-#ifdef CONFIG_MACB
- at91_gmac_hw_init();
- at91_macb_hw_init();
-#endif
return 0;
}
return 0;
}
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_MACB
- macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
- macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
-#endif
- return 0;
-}
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int board_mmc_init(bd_t *bis)
-{
- atmel_mci_init((void *)ATMEL_BASE_MCI0);
-
- return 0;
-}
-#endif
-
/* SPL */
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
#ifdef CONFIG_SYS_USE_MMC
+#ifdef CONFIG_GENERIC_ATMEL_MCI
sama5d3_xplained_mci0_hw_init();
+#endif
#elif CONFIG_SYS_USE_NANDFLASH
sama5d3_xplained_nand_hw_init();
#endif
*/
#include <common.h>
-#include <mmc.h>
#include <asm/io.h>
#include <asm/arch/sama5d3_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
+#include <debug_uart.h>
#include <lcd.h>
#include <linux/ctype.h>
#include <atmel_hlcdc.h>
-#include <atmel_mci.h>
#include <phy.h>
#include <micrel.h>
-#include <net.h>
-#include <netdev.h>
#include <spl.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/at91_wdt.h>
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-#include <asm/arch/atmel_usba_udc.h>
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
#ifdef CONFIG_GENERIC_ATMEL_MCI
static void sama5d3xek_mci_hw_init(void)
{
- at91_mci_hw_init();
-
at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */
}
#endif
#endif /* CONFIG_LCD_INFO */
#endif /* CONFIG_LCD */
-int board_early_init_f(void)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
{
- at91_periph_clk_enable(ATMEL_ID_PIOA);
- at91_periph_clk_enable(ATMEL_ID_PIOB);
- at91_periph_clk_enable(ATMEL_ID_PIOC);
- at91_periph_clk_enable(ATMEL_ID_PIOD);
- at91_periph_clk_enable(ATMEL_ID_PIOE);
-
at91_seriald_hw_init();
+}
+#endif
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
return 0;
}
+#endif
int board_init(void)
{
#ifdef CONFIG_CMD_USB
sama5d3xek_usb_hw_init();
#endif
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
- at91_udp_hw_init();
-#endif
#ifdef CONFIG_GENERIC_ATMEL_MCI
sama5d3xek_mci_hw_init();
#endif
-#ifdef CONFIG_ATMEL_SPI
- at91_spi0_hw_init(1 << 0);
-#endif
-#ifdef CONFIG_MACB
- if (has_emac())
- at91_macb_hw_init();
- if (has_gmac())
- at91_gmac_hw_init();
-#endif
#ifdef CONFIG_LCD
if (has_lcdc())
sama5d3xek_lcd_hw_init();
return 0;
}
-int board_phy_config(struct phy_device *phydev)
-{
- /* board specific timings for GMAC */
- if (has_gmac()) {
- /* rx data delay */
- ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
- 0x2222);
- /* tx data delay */
- ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
- 0x2222);
- /* rx/tx clock delay */
- ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
- 0xf2f4);
- }
-
- /* always run the PHY's config routine */
- if (phydev->drv->config)
- return phydev->drv->config(phydev);
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-
-#ifdef CONFIG_MACB
- if (has_emac())
- rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
- if (has_gmac())
- rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
-#endif
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
- usba_udc_probe(&pdata);
-#ifdef CONFIG_USB_ETH_RNDIS
- usb_eth_initialize(bis);
-#endif
-#endif
-
- return rc;
-}
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int board_mmc_init(bd_t *bis)
-{
- int rc = 0;
-
- rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);
-
- return rc;
-}
-#endif
-
-/* SPI chip select control */
-#ifdef CONFIG_ATMEL_SPI
-#include <spi.h>
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 && cs < 4;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- switch (slave->cs) {
- case 0:
- at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
- case 1:
- at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
- case 2:
- at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
- case 3:
- at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
- default:
- break;
- }
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- switch (slave->cs) {
- case 0:
- at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
- case 1:
- at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
- case 2:
- at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
- case 3:
- at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
- default:
- break;
- }
-}
-#endif /* CONFIG_ATMEL_SPI */
-
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
-#ifdef CONFIG_SYS_USE_MMC
- sama5d3xek_mci_hw_init();
-#elif CONFIG_SYS_USE_NANDFLASH
+#if CONFIG_SYS_USE_NANDFLASH
sama5d3xek_nand_hw_init();
-#elif CONFIG_SYS_USE_SERIALFLASH
- at91_spi0_hw_init(1 << 0);
#endif
}
#
obj-y += ls1021aiot.o
-obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
obj-$(CONFIG_ARMV7_PSCI) += psci.o
obj-y += ls1021aqds.o
obj-y += ddr.o
obj-y += eth.o
-obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
obj-$(CONFIG_ARMV7_PSCI) += psci.o
#
obj-y += ls1021atwr.o
-obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
obj-$(CONFIG_ARMV7_PSCI) += psci.o
#
obj-y := colibri_vf.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
#include <mmc.h>
#include <fdt_support.h>
#include <fsl_esdhc.h>
+#include <fsl_dcu_fb.h>
#include <jffs2/load_kernel.h>
#include <miiphy.h>
#include <mtd_node.h>
}
#endif
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+static void setup_iomux_fsl_dcu(void)
+{
+ static const iomux_v3_cfg_t dcu0_pads[] = {
+ VF610_PAD_PTE0__DCU0_HSYNC,
+ VF610_PAD_PTE1__DCU0_VSYNC,
+ VF610_PAD_PTE2__DCU0_PCLK,
+ VF610_PAD_PTE4__DCU0_DE,
+ VF610_PAD_PTE5__DCU0_R0,
+ VF610_PAD_PTE6__DCU0_R1,
+ VF610_PAD_PTE7__DCU0_R2,
+ VF610_PAD_PTE8__DCU0_R3,
+ VF610_PAD_PTE9__DCU0_R4,
+ VF610_PAD_PTE10__DCU0_R5,
+ VF610_PAD_PTE11__DCU0_R6,
+ VF610_PAD_PTE12__DCU0_R7,
+ VF610_PAD_PTE13__DCU0_G0,
+ VF610_PAD_PTE14__DCU0_G1,
+ VF610_PAD_PTE15__DCU0_G2,
+ VF610_PAD_PTE16__DCU0_G3,
+ VF610_PAD_PTE17__DCU0_G4,
+ VF610_PAD_PTE18__DCU0_G5,
+ VF610_PAD_PTE19__DCU0_G6,
+ VF610_PAD_PTE20__DCU0_G7,
+ VF610_PAD_PTE21__DCU0_B0,
+ VF610_PAD_PTE22__DCU0_B1,
+ VF610_PAD_PTE23__DCU0_B2,
+ VF610_PAD_PTE24__DCU0_B3,
+ VF610_PAD_PTE25__DCU0_B4,
+ VF610_PAD_PTE26__DCU0_B5,
+ VF610_PAD_PTE27__DCU0_B6,
+ VF610_PAD_PTE28__DCU0_B7,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads));
+}
+
+static void setup_tcon(void)
+{
+ setbits_le32(TCON0_BASE_ADDR, (1 << 29));
+}
+#endif
+
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{ESDHC1_BASE_ADDR},
CCM_CSCDR3_NFC_PRE_DIV(3));
clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
CCM_CSCMR2_RMII_CLK_SEL(2));
+
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+ setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK);
+ setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK);
+#endif
}
static void mscm_init(void)
setup_iomux_dspi();
#endif
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+ setup_tcon();
+ setup_iomux_fsl_dcu();
+#endif
+
return 0;
}
{
struct src *src = (struct src *)SRC_BASE_ADDR;
- /* Default memory arguments */
- if (!getenv("memargs")) {
- switch (gd->ram_size) {
- case 0x08000000:
- /* 128 MB */
- setenv("memargs", "mem=128M");
- break;
- case 0x10000000:
- /* 256 MB */
- setenv("memargs", "mem=256M");
- break;
- default:
- printf("Failed detecting RAM size.\n");
- }
- }
-
if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
== SRC_SBMR2_BMOD_SERIAL) {
printf("Serial Downloader recovery mode, disable autoboot\n");
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
+ int ret = 0;
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
static struct node_info nodes[] = {
{ "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */
puts(" Updating MTD partitions...\n");
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+ ret = fsl_dcu_fixedfb_setup(blob);
+ if (ret)
+ return ret;
+#endif
return ft_common_board_setup(blob, bd);
}
--- /dev/null
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * FSL DCU platform driver
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include "div64.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ unsigned long long div;
+
+ clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL);
+ clrsetbits_le32(&ccm->cscdr3,
+ CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN,
+ CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN);
+ div = (unsigned long long)(PLL1_PFD2_FREQ / 1000);
+ do_div(div, pixclock);
+
+ return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+ const char *port,
+ struct fb_videomode *dcu_fb_videomode)
+{
+ fsl_dcu_init(xres, yres, 32);
+
+ return 0;
+}
help
Enable the "icache" and "dcache" commands
+config CMD_LED
+ bool "led"
+ default y if LED
+ help
+ Enable the 'led' command which allows for control of LEDs supported
+ by the board. The LEDs can be listed with 'led list' and controlled
+ with led on/off/togle/blink. Any LED drivers can be controlled with
+ this command, e.g. led_gpio.
+
config CMD_TIME
bool "time"
help
obj-$(CONFIG_CMD_JFFS2) += jffs2.o
obj-$(CONFIG_CMD_CRAMFS) += cramfs.o
obj-$(CONFIG_CMD_LDRINFO) += ldrinfo.o
-obj-$(CONFIG_LED_STATUS_CMD) += led.o
+obj-$(CONFIG_LED_STATUS_CMD) += legacy_led.o
+obj-$(CONFIG_CMD_LED) += led.o
obj-$(CONFIG_CMD_LICENSE) += license.o
obj-y += load.o
obj-$(CONFIG_LOGBUFFER) += log.o
/*
- * (C) Copyright 2010
- * Jason Kridner <jkridner@beagleboard.org>
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
*
- * Based on cmd_led.c patch from:
- * http://www.mail-archive.com/u-boot@lists.denx.de/msg06873.html
- * (C) Copyright 2008
- * Ulf Samuelsson <ulf.samuelsson@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <config.h>
#include <command.h>
-#include <status_led.h>
-
-struct led_tbl_s {
- char *string; /* String for use in the command */
- led_id_t mask; /* Mask used for calling __led_set() */
- void (*off)(void); /* Optional function for turning LED off */
- void (*on)(void); /* Optional function for turning LED on */
- void (*toggle)(void);/* Optional function for toggling LED */
-};
+#include <dm.h>
+#include <led.h>
+#include <dm/uclass-internal.h>
-typedef struct led_tbl_s led_tbl_t;
+#define LED_TOGGLE LEDST_COUNT
-static const led_tbl_t led_commands[] = {
-#ifdef CONFIG_LED_STATUS_BOARD_SPECIFIC
-#ifdef CONFIG_LED_STATUS0
- { "0", CONFIG_LED_STATUS_BIT, NULL, NULL, NULL },
-#endif
-#ifdef CONFIG_LED_STATUS1
- { "1", CONFIG_LED_STATUS_BIT1, NULL, NULL, NULL },
-#endif
-#ifdef CONFIG_LED_STATUS2
- { "2", CONFIG_LED_STATUS_BIT2, NULL, NULL, NULL },
-#endif
-#ifdef CONFIG_LED_STATUS3
- { "3", CONFIG_LED_STATUS_BIT3, NULL, NULL, NULL },
-#endif
-#ifdef CONFIG_LED_STATUS4
- { "4", CONFIG_LED_STATUS_BIT4, NULL, NULL, NULL },
-#endif
-#ifdef CONFIG_LED_STATUS5
- { "5", CONFIG_LED_STATUS_BIT5, NULL, NULL, NULL },
-#endif
-#endif
-#ifdef CONFIG_LED_STATUS_GREEN
- { "green", CONFIG_LED_STATUS_GREEN, green_led_off, green_led_on, NULL },
-#endif
-#ifdef CONFIG_LED_STATUS_YELLOW
- { "yellow", CONFIG_LED_STATUS_YELLOW, yellow_led_off, yellow_led_on,
- NULL },
-#endif
-#ifdef CONFIG_LED_STATUS_RED
- { "red", CONFIG_LED_STATUS_RED, red_led_off, red_led_on, NULL },
-#endif
-#ifdef CONFIG_LED_STATUS_BLUE
- { "blue", CONFIG_LED_STATUS_BLUE, blue_led_off, blue_led_on, NULL },
+static const char *const state_label[] = {
+ [LEDST_OFF] = "off",
+ [LEDST_ON] = "on",
+ [LEDST_TOGGLE] = "toggle",
+#ifdef CONFIG_LED_BLINK
+ [LEDST_BLINK] = "blink",
#endif
- { NULL, 0, NULL, NULL, NULL }
};
-enum led_cmd { LED_ON, LED_OFF, LED_TOGGLE, LED_BLINK };
-
-enum led_cmd get_led_cmd(char *var)
+enum led_state_t get_led_cmd(char *var)
{
- if (strcmp(var, "off") == 0)
- return LED_OFF;
- if (strcmp(var, "on") == 0)
- return LED_ON;
- if (strcmp(var, "toggle") == 0)
- return LED_TOGGLE;
- if (strcmp(var, "blink") == 0)
- return LED_BLINK;
+ int i;
+
+ for (i = 0; i < LEDST_COUNT; i++) {
+ if (!strncmp(var, state_label[i], strlen(var)))
+ return i;
+ }
return -1;
}
-/*
- * LED drivers providing a blinking LED functionality, like the
- * PCA9551, can override this empty weak function
- */
-void __weak __led_blink(led_id_t mask, int freq)
+static int show_led_state(struct udevice *dev)
{
+ int ret;
+
+ ret = led_get_state(dev);
+ if (ret >= LEDST_COUNT)
+ ret = -EINVAL;
+ if (ret >= 0)
+ printf("%s\n", state_label[ret]);
+
+ return ret;
+}
+
+static int list_leds(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ for (uclass_find_first_device(UCLASS_LED, &dev);
+ dev;
+ uclass_find_next_device(&dev)) {
+ struct led_uc_plat *plat = dev_get_uclass_platdata(dev);
+
+ if (!plat->label)
+ continue;
+ printf("%-15s ", plat->label);
+ if (device_active(dev)) {
+ ret = show_led_state(dev);
+ if (ret < 0)
+ printf("Error %d\n", ret);
+ } else {
+ printf("<inactive>\n");
+ }
+ }
+
+ return 0;
}
-int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_led(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- int i, match = 0;
- enum led_cmd cmd;
- int freq;
+ enum led_state_t cmd;
+ const char *led_label;
+ struct udevice *dev;
+#ifdef CONFIG_LED_BLINK
+ int freq_ms = 0;
+#endif
+ int ret;
/* Validate arguments */
- if ((argc < 3) || (argc > 4))
+ if (argc < 2)
return CMD_RET_USAGE;
+ led_label = argv[1];
+ if (*led_label == 'l')
+ return list_leds();
- cmd = get_led_cmd(argv[2]);
- if (cmd < 0) {
+ cmd = argc > 2 ? get_led_cmd(argv[2]) : LEDST_COUNT;
+ if (cmd < 0)
return CMD_RET_USAGE;
+#ifdef CONFIG_LED_BLINK
+ if (cmd == LEDST_BLINK) {
+ if (argc < 4)
+ return CMD_RET_USAGE;
+ freq_ms = simple_strtoul(argv[3], NULL, 10);
}
-
- for (i = 0; led_commands[i].string; i++) {
- if ((strcmp("all", argv[1]) == 0) ||
- (strcmp(led_commands[i].string, argv[1]) == 0)) {
- match = 1;
- switch (cmd) {
- case LED_ON:
- if (led_commands[i].on)
- led_commands[i].on();
- else
- __led_set(led_commands[i].mask,
- CONFIG_LED_STATUS_ON);
- break;
- case LED_OFF:
- if (led_commands[i].off)
- led_commands[i].off();
- else
- __led_set(led_commands[i].mask,
- CONFIG_LED_STATUS_OFF);
- break;
- case LED_TOGGLE:
- if (led_commands[i].toggle)
- led_commands[i].toggle();
- else
- __led_toggle(led_commands[i].mask);
- break;
- case LED_BLINK:
- if (argc != 4)
- return CMD_RET_USAGE;
-
- freq = simple_strtoul(argv[3], NULL, 10);
- __led_blink(led_commands[i].mask, freq);
- }
- /* Need to set only 1 led if led_name wasn't 'all' */
- if (strcmp("all", argv[1]) != 0)
- break;
- }
+#endif
+ ret = led_get_by_label(led_label, &dev);
+ if (ret) {
+ printf("LED '%s' not found (err=%d)\n", led_label, ret);
+ return CMD_RET_FAILURE;
}
-
- /* If we ran out of matches, print Usage */
- if (!match) {
- return CMD_RET_USAGE;
+ switch (cmd) {
+ case LEDST_OFF:
+ case LEDST_ON:
+ case LEDST_TOGGLE:
+ ret = led_set_state(dev, cmd);
+ break;
+#ifdef CONFIG_LED_BLINK
+ case LEDST_BLINK:
+ ret = led_set_period(dev, freq_ms);
+ if (!ret)
+ ret = led_set_state(dev, LEDST_BLINK);
+ break;
+#endif
+ case LEDST_COUNT:
+ printf("LED '%s': ", led_label);
+ ret = show_led_state(dev);
+ break;
+ }
+ if (ret < 0) {
+ printf("LED '%s' operation failed (err=%d)\n", led_label, ret);
+ return CMD_RET_FAILURE;
}
return 0;
}
+#ifdef CONFIG_LED_BLINK
+#define BLINK "|blink [blink-freq in ms]"
+#else
+#define BLINK ""
+#endif
+
U_BOOT_CMD(
led, 4, 1, do_led,
- "["
-#ifdef CONFIG_LED_STATUS_BOARD_SPECIFIC
-#ifdef CONFIG_LED_STATUS0
- "0|"
-#endif
-#ifdef CONFIG_LED_STATUS1
- "1|"
-#endif
-#ifdef CONFIG_LED_STATUS2
- "2|"
-#endif
-#ifdef CONFIG_LED_STATUS3
- "3|"
-#endif
-#ifdef CONFIG_LED_STATUS4
- "4|"
-#endif
-#ifdef CONFIG_LED_STATUS5
- "5|"
-#endif
-#endif
-#ifdef CONFIG_LED_STATUS_GREEN
- "green|"
-#endif
-#ifdef CONFIG_LED_STATUS_YELLOW
- "yellow|"
-#endif
-#ifdef CONFIG_LED_STATUS_RED
- "red|"
-#endif
-#ifdef CONFIG_LED_STATUS_BLUE
- "blue|"
-#endif
- "all] [on|off|toggle|blink] [blink-freq in ms]",
- "[led_name] [on|off|toggle|blink] sets or clears led(s)"
+ "manage LEDs",
+ "<led_label> on|off|toggle" BLINK "\tChange LED state\n"
+ "led [<led_label>\tGet LED state\n"
+ "led list\t\tshow a list of LEDs"
);
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Jason Kridner <jkridner@beagleboard.org>
+ *
+ * Based on cmd_led.c patch from:
+ * http://www.mail-archive.com/u-boot@lists.denx.de/msg06873.html
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf.samuelsson@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <status_led.h>
+
+struct led_tbl_s {
+ char *string; /* String for use in the command */
+ led_id_t mask; /* Mask used for calling __led_set() */
+ void (*off)(void); /* Optional function for turning LED off */
+ void (*on)(void); /* Optional function for turning LED on */
+ void (*toggle)(void);/* Optional function for toggling LED */
+};
+
+typedef struct led_tbl_s led_tbl_t;
+
+static const led_tbl_t led_commands[] = {
+#ifdef CONFIG_LED_STATUS_BOARD_SPECIFIC
+#ifdef CONFIG_LED_STATUS0
+ { "0", CONFIG_LED_STATUS_BIT, NULL, NULL, NULL },
+#endif
+#ifdef CONFIG_LED_STATUS1
+ { "1", CONFIG_LED_STATUS_BIT1, NULL, NULL, NULL },
+#endif
+#ifdef CONFIG_LED_STATUS2
+ { "2", CONFIG_LED_STATUS_BIT2, NULL, NULL, NULL },
+#endif
+#ifdef CONFIG_LED_STATUS3
+ { "3", CONFIG_LED_STATUS_BIT3, NULL, NULL, NULL },
+#endif
+#ifdef CONFIG_LED_STATUS4
+ { "4", CONFIG_LED_STATUS_BIT4, NULL, NULL, NULL },
+#endif
+#ifdef CONFIG_LED_STATUS5
+ { "5", CONFIG_LED_STATUS_BIT5, NULL, NULL, NULL },
+#endif
+#endif
+#ifdef CONFIG_LED_STATUS_GREEN
+ { "green", CONFIG_LED_STATUS_GREEN, green_led_off, green_led_on, NULL },
+#endif
+#ifdef CONFIG_LED_STATUS_YELLOW
+ { "yellow", CONFIG_LED_STATUS_YELLOW, yellow_led_off, yellow_led_on,
+ NULL },
+#endif
+#ifdef CONFIG_LED_STATUS_RED
+ { "red", CONFIG_LED_STATUS_RED, red_led_off, red_led_on, NULL },
+#endif
+#ifdef CONFIG_LED_STATUS_BLUE
+ { "blue", CONFIG_LED_STATUS_BLUE, blue_led_off, blue_led_on, NULL },
+#endif
+ { NULL, 0, NULL, NULL, NULL }
+};
+
+enum led_cmd { LED_ON, LED_OFF, LED_TOGGLE, LED_BLINK };
+
+enum led_cmd get_led_cmd(char *var)
+{
+ if (strcmp(var, "off") == 0)
+ return LED_OFF;
+ if (strcmp(var, "on") == 0)
+ return LED_ON;
+ if (strcmp(var, "toggle") == 0)
+ return LED_TOGGLE;
+ if (strcmp(var, "blink") == 0)
+ return LED_BLINK;
+
+ return -1;
+}
+
+/*
+ * LED drivers providing a blinking LED functionality, like the
+ * PCA9551, can override this empty weak function
+ */
+void __weak __led_blink(led_id_t mask, int freq)
+{
+}
+
+int do_legacy_led(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int i, match = 0;
+ enum led_cmd cmd;
+ int freq;
+
+ /* Validate arguments */
+ if ((argc < 3) || (argc > 4))
+ return CMD_RET_USAGE;
+
+ cmd = get_led_cmd(argv[2]);
+ if (cmd < 0) {
+ return CMD_RET_USAGE;
+ }
+
+ for (i = 0; led_commands[i].string; i++) {
+ if ((strcmp("all", argv[1]) == 0) ||
+ (strcmp(led_commands[i].string, argv[1]) == 0)) {
+ match = 1;
+ switch (cmd) {
+ case LED_ON:
+ if (led_commands[i].on)
+ led_commands[i].on();
+ else
+ __led_set(led_commands[i].mask,
+ CONFIG_LED_STATUS_ON);
+ break;
+ case LED_OFF:
+ if (led_commands[i].off)
+ led_commands[i].off();
+ else
+ __led_set(led_commands[i].mask,
+ CONFIG_LED_STATUS_OFF);
+ break;
+ case LED_TOGGLE:
+ if (led_commands[i].toggle)
+ led_commands[i].toggle();
+ else
+ __led_toggle(led_commands[i].mask);
+ break;
+ case LED_BLINK:
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ freq = simple_strtoul(argv[3], NULL, 10);
+ __led_blink(led_commands[i].mask, freq);
+ }
+ /* Need to set only 1 led if led_name wasn't 'all' */
+ if (strcmp("all", argv[1]) != 0)
+ break;
+ }
+ }
+
+ /* If we ran out of matches, print Usage */
+ if (!match) {
+ return CMD_RET_USAGE;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ led, 4, 1, do_legacy_led,
+ "["
+#ifdef CONFIG_LED_STATUS_BOARD_SPECIFIC
+#ifdef CONFIG_LED_STATUS0
+ "0|"
+#endif
+#ifdef CONFIG_LED_STATUS1
+ "1|"
+#endif
+#ifdef CONFIG_LED_STATUS2
+ "2|"
+#endif
+#ifdef CONFIG_LED_STATUS3
+ "3|"
+#endif
+#ifdef CONFIG_LED_STATUS4
+ "4|"
+#endif
+#ifdef CONFIG_LED_STATUS5
+ "5|"
+#endif
+#endif
+#ifdef CONFIG_LED_STATUS_GREEN
+ "green|"
+#endif
+#ifdef CONFIG_LED_STATUS_YELLOW
+ "yellow|"
+#endif
+#ifdef CONFIG_LED_STATUS_RED
+ "red|"
+#endif
+#ifdef CONFIG_LED_STATUS_BLUE
+ "blue|"
+#endif
+ "all] [on|off|toggle|blink] [blink-freq in ms]",
+ "[led_name] [on|off|toggle|blink] sets or clears led(s)"
+);
* scsi_detect_dev - Detect scsi device
*
* @target: target id
+ * @lun: target lun
* @dev_desc: block device description
*
* The scsi_detect_dev detects and fills a dev_desc structure when the device is
- * detected. The LUN number is taken from the struct blk_desc *dev_desc.
+ * detected.
*
* Return: 0 on success, error value otherwise
*/
-static int scsi_detect_dev(int target, struct blk_desc *dev_desc)
+static int scsi_detect_dev(int target, int lun, struct blk_desc *dev_desc)
{
unsigned char perq, modi;
lbaint_t capacity;
ccb *pccb = (ccb *)&tempccb;
pccb->target = target;
- pccb->lun = dev_desc->lun;
+ pccb->lun = lun;
pccb->pdata = (unsigned char *)&tempbuff;
pccb->datalen = 512;
scsi_setup_inquiry(pccb);
dev_desc->blksz = blksz;
dev_desc->log2blksz = LOG2(dev_desc->blksz);
dev_desc->type = perq;
- part_init(&dev_desc[0]);
removable:
return 0;
}
for (lun = 0; lun < plat->max_lun; lun++) {
struct udevice *bdev; /* block device */
/* block device description */
+ struct blk_desc _bd;
struct blk_desc *bdesc;
char str[10];
+ scsi_init_dev_desc_priv(&_bd);
+ ret = scsi_detect_dev(i, lun, &_bd);
+ if (ret)
+ /*
+ * no device detected?
+ * check the next lun.
+ */
+ continue;
+
/*
* Create only one block device and do detection
* to make sure that there won't be a lot of
*/
snprintf(str, sizeof(str), "id%dlun%d", i, lun);
ret = blk_create_devicef(dev, "scsi_blk",
- str, IF_TYPE_SCSI,
- -1, 0, 0, &bdev);
+ str, IF_TYPE_SCSI,
+ -1,
+ _bd.blksz,
+ _bd.blksz * _bd.lba,
+ &bdev);
if (ret) {
debug("Can't create device\n");
return ret;
}
- bdesc = dev_get_uclass_platdata(bdev);
- scsi_init_dev_desc_priv(bdesc);
+ bdesc = dev_get_uclass_platdata(bdev);
+ bdesc->target = i;
bdesc->lun = lun;
- ret = scsi_detect_dev(i, bdesc);
- if (ret) {
- device_unbind(bdev);
- continue;
- }
+ bdesc->removable = _bd.removable;
+ bdesc->type = _bd.type;
+ memcpy(&bdesc->vendor, &_bd.vendor,
+ sizeof(_bd.vendor));
+ memcpy(&bdesc->product, &_bd.product,
+ sizeof(_bd.product));
+ memcpy(&bdesc->revision, &_bd.revision,
+ sizeof(_bd.revision));
+ part_init(bdesc);
if (mode == 1) {
printf(" Device %d: ", 0);
scsi_max_devs = 0;
for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
for (lun = 0; lun < CONFIG_SYS_SCSI_MAX_LUN; lun++) {
- scsi_dev_desc[scsi_max_devs].lun = lun;
- ret = scsi_detect_dev(i, &scsi_dev_desc[scsi_max_devs]);
+ ret = scsi_detect_dev(i, lun,
+ &scsi_dev_desc[scsi_max_devs]);
if (ret)
continue;
+ part_init(&scsi_dev_desc[scsi_max_devs]);
if (mode == 1) {
printf(" Device %d: ", 0);
CONFIG_G_DNL_VENDOR_NUM=0x1b67
CONFIG_G_DNL_PRODUCT_NUM=0x4000
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_FSL_DCU_FB=y
+CONFIG_SYS_CONSOLE_FG_COL=0x00
+CONFIG_SYS_CONSOLE_BG_COL=0x00
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xffffee00
+CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xffffee00
+CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD_NOR_FLASH=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xffffee00
+CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD_NOR_FLASH=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xffffee00
+CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD_NOR_FLASH=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xffffee00
+CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_LCD=y
-CONFIG_OF_LIBFDT=y
CONFIG_CROS_EC_KEYB=y
CONFIG_I8042_KEYB=y
CONFIG_LED=y
+CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_DM_MAILBOX=y
CONFIG_SANDBOX_MBOX=y
CONFIG_CROS_EC_KEYB=y
CONFIG_I8042_KEYB=y
CONFIG_LED=y
+CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_CROS_EC_KEYB=y
CONFIG_I8042_KEYB=y
CONFIG_LED=y
+CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_DM_MAILBOX=y
CONFIG_SANDBOX_MBOX=y
--- /dev/null
+Atmel HLCDC Framebuffer
+-----------------------------------------------------
+Required properties:
+- compatible :
+ "atmel,sama5d2-hlcdc", "atmel,at91sam9x5-hlcdc".
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- clocks: phandles to input clocks.
+- atmel,vl-bpix: Bits per pixel.
+- atmel,output-mode: LCD Controller Output Mode,
+ The unit is bits per pixel, there are four values,
+ <12>, <16>, <18>, <24>, the default value is <24>.
+- atmel,guard-time: lcd guard time (Delay in frame periods).
+- display-timings: please refer the displaymode.txt.
+
+Example:
+hlcdc: hlcdc@f0000000 {
+ u-boot,dm-pre-reloc;
+ compatible = "atmel,sama5d2-hlcdc";
+ reg = <0xf0000000 0x2000>;
+ clocks = <&lcdc_clk>;
+ atmel,vl-bpix = <4>;
+ atmel,output-mode = <24>;
+ atmel,guard-time = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>;
+ status = "okay";
+
+ display-timings {
+ 480x272 {
+ clock-frequency = <9000000>;
+ hactive = <480>;
+ vactive = <272>;
+ hsync-len = <41>;
+ hfront-porch = <2>;
+ hback-porch = <2>;
+ vfront-porch = <2>;
+ vback-porch = <2>;
+ vsync-len = <11>;
+ };
+ };
+};
can provide access to board-specific LEDs. Use of the device tree
for configuration is encouraged.
+config LED_BLINK
+ bool "Support LED blinking"
+ depends on LED
+ help
+ Some drivers can support automatic blinking of LEDs with a given
+ period, without needing timers or extra code to handle the timing.
+ This option enables support for this which adds slightly to the
+ code size.
+
config SPL_LED
bool "Enable LED support in SPL"
depends on SPL && SPL_DM
If this is acceptable and you have a need to use LEDs in SPL,
enable this option. You will need to enable device tree in SPL
for this to work.
+
config LED_GPIO
bool "LED support for GPIO-connected LEDs"
depends on LED && DM_GPIO
if (ret)
return ret;
uclass_foreach_dev(dev, uc) {
- struct led_uclass_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct led_uc_plat *uc_plat = dev_get_uclass_platdata(dev);
/* Ignore the top-level LED node */
if (uc_plat->label && !strcmp(label, uc_plat->label))
return -ENODEV;
}
-int led_set_on(struct udevice *dev, int on)
+int led_set_state(struct udevice *dev, enum led_state_t state)
{
struct led_ops *ops = led_get_ops(dev);
- if (!ops->set_on)
+ if (!ops->set_state)
return -ENOSYS;
- return ops->set_on(dev, on);
+ return ops->set_state(dev, state);
}
+enum led_state_t led_get_state(struct udevice *dev)
+{
+ struct led_ops *ops = led_get_ops(dev);
+
+ if (!ops->get_state)
+ return -ENOSYS;
+
+ return ops->get_state(dev);
+}
+
+#ifdef CONFIG_LED_BLINK
+int led_set_period(struct udevice *dev, int period_ms)
+{
+ struct led_ops *ops = led_get_ops(dev);
+
+ if (!ops->set_period)
+ return -ENOSYS;
+
+ return ops->set_period(dev, period_ms);
+}
+#endif
+
UCLASS_DRIVER(led) = {
.id = UCLASS_LED,
.name = "led",
- .per_device_platdata_auto_alloc_size = sizeof(struct led_uclass_plat),
+ .per_device_platdata_auto_alloc_size = sizeof(struct led_uc_plat),
};
struct gpio_desc gpio;
};
-static int gpio_led_set_on(struct udevice *dev, int on)
+static int gpio_led_set_state(struct udevice *dev, enum led_state_t state)
{
struct led_gpio_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if (!dm_gpio_is_valid(&priv->gpio))
+ return -EREMOTEIO;
+ switch (state) {
+ case LEDST_OFF:
+ case LEDST_ON:
+ break;
+ case LEDST_TOGGLE:
+ ret = dm_gpio_get_value(&priv->gpio);
+ if (ret < 0)
+ return ret;
+ state = !ret;
+ break;
+ default:
+ return -ENOSYS;
+ }
+
+ return dm_gpio_set_value(&priv->gpio, state);
+}
+
+static enum led_state_t gpio_led_get_state(struct udevice *dev)
+{
+ struct led_gpio_priv *priv = dev_get_priv(dev);
+ int ret;
if (!dm_gpio_is_valid(&priv->gpio))
return -EREMOTEIO;
+ ret = dm_gpio_get_value(&priv->gpio);
+ if (ret < 0)
+ return ret;
- return dm_gpio_set_value(&priv->gpio, on);
+ return ret ? LEDST_ON : LEDST_OFF;
}
static int led_gpio_probe(struct udevice *dev)
{
- struct led_uclass_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct led_uc_plat *uc_plat = dev_get_uclass_platdata(dev);
struct led_gpio_priv *priv = dev_get_priv(dev);
/* Ignore the top-level LED node */
for (node = fdt_first_subnode(blob, dev_of_offset(parent));
node > 0;
node = fdt_next_subnode(blob, node)) {
- struct led_uclass_plat *uc_plat;
+ struct led_uc_plat *uc_plat;
const char *label;
label = fdt_getprop(blob, node, "label", NULL);
}
static const struct led_ops gpio_led_ops = {
- .set_on = gpio_led_set_on,
+ .set_state = gpio_led_set_state,
+ .get_state = gpio_led_get_state,
};
static const struct udevice_id led_gpio_ids[] = {
The devices provide a simple interface to start up the display,
read display information and enable it.
+config ATMEL_HLCD
+ bool "Enable ATMEL video support using HLCDC"
+ depends on DM_VIDEO
+ help
+ HLCDC supports video output to an attached LCD panel.
+
config VIDEO_BROADWELL_IGD
bool "Enable Intel Broadwell integrated graphics device"
depends on X86
a special tool which configures the VGA ROM, but the graphics
resolution can be selected in U-Boot.
+config VIDEO_FSL_DCU_FB
+ bool "Enable Freescale Display Control Unit"
+ depends on VIDEO
+ help
+ This enables support for Freescale Display Control Unit (DCU4)
+ module found on Freescale Vybrid and QorIQ family of SoCs.
+
+config VIDEO_FSL_DCU_MAX_FB_SIZE_MB
+ int "Freescale DCU framebuffer size"
+ depends on VIDEO_FSL_DCU_FB
+ default 4194304
+ help
+ Set maximum framebuffer size to be used for Freescale Display
+ Controller Unit (DCU4).
+
config VIDEO_ROCKCHIP
bool "Enable Rockchip video support"
depends on DM_VIDEO
obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o
obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
-obj-$(CONFIG_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
obj-$(CONFIG_L5F31188) += l5f31188.o
obj-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o
obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
+#include <clk.h>
+#include <dm.h>
+#include <fdtdec.h>
#include <lcd.h>
+#include <video.h>
+#include <wait_bit.h>
#include <atmel_hlcdc.h>
#if defined(CONFIG_LCD_LOGO)
#include <bmp_logo.h>
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_DM_VIDEO
+
/* configurable parameters */
#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
#define ATMEL_LCDC_DMA_BURST_LEN 8
#define ATMEL_LCDC_FIFO_SIZE 512
-#define lcdc_readl(reg) __raw_readl((reg))
-#define lcdc_writel(reg, val) __raw_writel((val), (reg))
-
/*
* the CLUT register map as following
* RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0)
*/
void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
{
- lcdc_writel(((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk)
- | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk)
- | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk),
- panel_info.mmio + ATMEL_LCDC_LUT(regno));
+ writel(panel_info.mmio + ATMEL_LCDC_LUT(regno),
+ ((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk)
+ | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk)
+ | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk));
}
ushort *configuration_get_cmap(void)
unsigned long value;
struct lcd_dma_desc *desc;
struct atmel_hlcd_regs *regs;
+ int ret;
if (!has_lcdc())
return; /* No lcdc */
regs = (struct atmel_hlcd_regs *)panel_info.mmio;
/* Disable DISP signal */
- lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_DISPDIS);
- while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS))
- udelay(1);
+ writel(LCDC_LCDDIS_DISPDIS, ®s->lcdc_lcddis);
+ ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
+ false, 1000, false);
+ if (ret)
+ printf("%s: %d: Timeout!\n", __func__, __LINE__);
/* Disable synchronization */
- lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_SYNCDIS);
- while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS))
- udelay(1);
+ writel(LCDC_LCDDIS_SYNCDIS, ®s->lcdc_lcddis);
+ ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
+ false, 1000, false);
+ if (ret)
+ printf("%s: %d: Timeout!\n", __func__, __LINE__);
/* Disable pixel clock */
- lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_CLKDIS);
- while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS))
- udelay(1);
+ writel(LCDC_LCDDIS_CLKDIS, ®s->lcdc_lcddis);
+ ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
+ false, 1000, false);
+ if (ret)
+ printf("%s: %d: Timeout!\n", __func__, __LINE__);
/* Disable PWM */
- lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_PWMDIS);
- while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
- udelay(1);
+ writel(LCDC_LCDDIS_PWMDIS, ®s->lcdc_lcddis);
+ ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
+ false, 1000, false);
+ if (ret)
+ printf("%s: %d: Timeout!\n", __func__, __LINE__);
/* Set pixel clock */
value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
if (value < 1) {
/* Using system clock as pixel clock */
- lcdc_writel(®s->lcdc_lcdcfg0,
- LCDC_LCDCFG0_CLKDIV(0)
- | LCDC_LCDCFG0_CGDISHCR
- | LCDC_LCDCFG0_CGDISHEO
- | LCDC_LCDCFG0_CGDISOVR1
- | LCDC_LCDCFG0_CGDISBASE
- | panel_info.vl_clk_pol
- | LCDC_LCDCFG0_CLKSEL);
+ writel(LCDC_LCDCFG0_CLKDIV(0)
+ | LCDC_LCDCFG0_CGDISHCR
+ | LCDC_LCDCFG0_CGDISHEO
+ | LCDC_LCDCFG0_CGDISOVR1
+ | LCDC_LCDCFG0_CGDISBASE
+ | panel_info.vl_clk_pol
+ | LCDC_LCDCFG0_CLKSEL,
+ ®s->lcdc_lcdcfg0);
} else {
- lcdc_writel(®s->lcdc_lcdcfg0,
- LCDC_LCDCFG0_CLKDIV(value - 2)
- | LCDC_LCDCFG0_CGDISHCR
- | LCDC_LCDCFG0_CGDISHEO
- | LCDC_LCDCFG0_CGDISOVR1
- | LCDC_LCDCFG0_CGDISBASE
- | panel_info.vl_clk_pol);
+ writel(LCDC_LCDCFG0_CLKDIV(value - 2)
+ | LCDC_LCDCFG0_CGDISHCR
+ | LCDC_LCDCFG0_CGDISHEO
+ | LCDC_LCDCFG0_CGDISOVR1
+ | LCDC_LCDCFG0_CGDISBASE
+ | panel_info.vl_clk_pol,
+ ®s->lcdc_lcdcfg0);
}
/* Initialize control register 5 */
value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
- lcdc_writel(®s->lcdc_lcdcfg5, value);
+ writel(value, ®s->lcdc_lcdcfg5);
/* Vertical & Horizontal Timing */
value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
- lcdc_writel(®s->lcdc_lcdcfg1, value);
+ writel(value, ®s->lcdc_lcdcfg1);
value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
- lcdc_writel(®s->lcdc_lcdcfg2, value);
+ writel(value, ®s->lcdc_lcdcfg2);
value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
- lcdc_writel(®s->lcdc_lcdcfg3, value);
+ writel(value, ®s->lcdc_lcdcfg3);
/* Display size */
value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
- lcdc_writel(®s->lcdc_lcdcfg4, value);
+ writel(value, ®s->lcdc_lcdcfg4);
- lcdc_writel(®s->lcdc_basecfg0,
- LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO);
+ writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
+ ®s->lcdc_basecfg0);
switch (NBITS(panel_info.vl_bpix)) {
case 16:
- lcdc_writel(®s->lcdc_basecfg1,
- LCDC_BASECFG1_RGBMODE_16BPP_RGB_565);
+ writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
+ ®s->lcdc_basecfg1);
break;
case 32:
- lcdc_writel(®s->lcdc_basecfg1,
- LCDC_BASECFG1_RGBMODE_24BPP_RGB_888);
+ writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
+ ®s->lcdc_basecfg1);
break;
default:
BUG();
break;
}
- lcdc_writel(®s->lcdc_basecfg2, LCDC_BASECFG2_XSTRIDE(0));
- lcdc_writel(®s->lcdc_basecfg3, 0);
- lcdc_writel(®s->lcdc_basecfg4, LCDC_BASECFG4_DMA);
+ writel(LCDC_BASECFG2_XSTRIDE(0), ®s->lcdc_basecfg2);
+ writel(0, ®s->lcdc_basecfg3);
+ writel(LCDC_BASECFG4_DMA, ®s->lcdc_basecfg4);
/* Disable all interrupts */
- lcdc_writel(®s->lcdc_lcdidr, ~0UL);
- lcdc_writel(®s->lcdc_baseidr, ~0UL);
+ writel(~0UL, ®s->lcdc_lcdidr);
+ writel(~0UL, ®s->lcdc_baseidr);
/* Setup the DMA descriptor, this descriptor will loop to itself */
desc = (struct lcd_dma_desc *)(lcdbase - 16);
/* Flush the DMA descriptor if we enabled dcache */
flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
- lcdc_writel(®s->lcdc_baseaddr, desc->address);
- lcdc_writel(®s->lcdc_basectrl, desc->control);
- lcdc_writel(®s->lcdc_basenext, desc->next);
- lcdc_writel(®s->lcdc_basecher, LCDC_BASECHER_CHEN |
- LCDC_BASECHER_UPDATEEN);
+ writel(desc->address, ®s->lcdc_baseaddr);
+ writel(desc->control, ®s->lcdc_basectrl);
+ writel(desc->next, ®s->lcdc_basenext);
+ writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
+ ®s->lcdc_basecher);
/* Enable LCD */
- value = lcdc_readl(®s->lcdc_lcden);
- lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_CLKEN);
- while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS))
- udelay(1);
- value = lcdc_readl(®s->lcdc_lcden);
- lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_SYNCEN);
- while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS))
- udelay(1);
- value = lcdc_readl(®s->lcdc_lcden);
- lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_DISPEN);
- while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS))
- udelay(1);
- value = lcdc_readl(®s->lcdc_lcden);
- lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_PWMEN);
- while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
- udelay(1);
+ value = readl(®s->lcdc_lcden);
+ writel(value | LCDC_LCDEN_CLKEN, ®s->lcdc_lcden);
+ ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
+ true, 1000, false);
+ if (ret)
+ printf("%s: %d: Timeout!\n", __func__, __LINE__);
+ value = readl(®s->lcdc_lcden);
+ writel(value | LCDC_LCDEN_SYNCEN, ®s->lcdc_lcden);
+ ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
+ true, 1000, false);
+ if (ret)
+ printf("%s: %d: Timeout!\n", __func__, __LINE__);
+ value = readl(®s->lcdc_lcden);
+ writel(value | LCDC_LCDEN_DISPEN, ®s->lcdc_lcden);
+ ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
+ true, 1000, false);
+ if (ret)
+ printf("%s: %d: Timeout!\n", __func__, __LINE__);
+ value = readl(®s->lcdc_lcden);
+ writel(value | LCDC_LCDEN_PWMEN, ®s->lcdc_lcden);
+ ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
+ true, 1000, false);
+ if (ret)
+ printf("%s: %d: Timeout!\n", __func__, __LINE__);
/* Enable flushing if we enabled dcache */
lcd_set_flush_dcache(1);
}
+
+#else
+
+enum {
+ LCD_MAX_WIDTH = 1024,
+ LCD_MAX_HEIGHT = 768,
+ LCD_MAX_LOG2_BPP = VIDEO_BPP16,
+};
+
+struct atmel_hlcdc_priv {
+ struct atmel_hlcd_regs *regs;
+ struct display_timing timing;
+ unsigned int vl_bpix;
+ unsigned int output_mode;
+ unsigned int guard_time;
+ ulong clk_rate;
+};
+
+static int at91_hlcdc_enable_clk(struct udevice *dev)
+{
+ struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
+ struct clk clk;
+ ulong clk_rate;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return -EINVAL;
+
+ ret = clk_enable(&clk);
+ if (ret)
+ return ret;
+
+ clk_rate = clk_get_rate(&clk);
+ if (!clk_rate) {
+ clk_disable(&clk);
+ return -ENODEV;
+ }
+
+ priv->clk_rate = clk_rate;
+
+ clk_free(&clk);
+
+ return 0;
+}
+
+static void atmel_hlcdc_init(struct udevice *dev)
+{
+ struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
+ struct atmel_hlcd_regs *regs = priv->regs;
+ struct display_timing *timing = &priv->timing;
+ struct lcd_dma_desc *desc;
+ unsigned long value, vl_clk_pol;
+ int ret;
+
+ /* Disable DISP signal */
+ writel(LCDC_LCDDIS_DISPDIS, ®s->lcdc_lcddis);
+ ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
+ false, 1000, false);
+ if (ret)
+ printf("%s: %d: Timeout!\n", __func__, __LINE__);
+ /* Disable synchronization */
+ writel(LCDC_LCDDIS_SYNCDIS, ®s->lcdc_lcddis);
+ ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
+ false, 1000, false);
+ if (ret)
+ printf("%s: %d: Timeout!\n", __func__, __LINE__);
+ /* Disable pixel clock */
+ writel(LCDC_LCDDIS_CLKDIS, ®s->lcdc_lcddis);
+ ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
+ false, 1000, false);
+ if (ret)
+ printf("%s: %d: Timeout!\n", __func__, __LINE__);
+ /* Disable PWM */
+ writel(LCDC_LCDDIS_PWMDIS, ®s->lcdc_lcddis);
+ ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
+ false, 1000, false);
+ if (ret)
+ printf("%s: %d: Timeout!\n", __func__, __LINE__);
+
+ /* Set pixel clock */
+ value = priv->clk_rate / timing->pixelclock.typ;
+ if (priv->clk_rate % timing->pixelclock.typ)
+ value++;
+
+ vl_clk_pol = 0;
+ if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+ vl_clk_pol = LCDC_LCDCFG0_CLKPOL;
+
+ if (value < 1) {
+ /* Using system clock as pixel clock */
+ writel(LCDC_LCDCFG0_CLKDIV(0)
+ | LCDC_LCDCFG0_CGDISHCR
+ | LCDC_LCDCFG0_CGDISHEO
+ | LCDC_LCDCFG0_CGDISOVR1
+ | LCDC_LCDCFG0_CGDISBASE
+ | vl_clk_pol
+ | LCDC_LCDCFG0_CLKSEL,
+ ®s->lcdc_lcdcfg0);
+
+ } else {
+ writel(LCDC_LCDCFG0_CLKDIV(value - 2)
+ | LCDC_LCDCFG0_CGDISHCR
+ | LCDC_LCDCFG0_CGDISHEO
+ | LCDC_LCDCFG0_CGDISOVR1
+ | LCDC_LCDCFG0_CGDISBASE
+ | vl_clk_pol,
+ ®s->lcdc_lcdcfg0);
+ }
+
+ /* Initialize control register 5 */
+ value = 0;
+
+ if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
+ value |= LCDC_LCDCFG5_HSPOL;
+ if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
+ value |= LCDC_LCDCFG5_VSPOL;
+
+ switch (priv->output_mode) {
+ case 12:
+ value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
+ break;
+ case 16:
+ value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
+ break;
+ case 18:
+ value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
+ break;
+ case 24:
+ value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
+ break;
+ default:
+ BUG();
+ break;
+ }
+
+ value |= LCDC_LCDCFG5_GUARDTIME(priv->guard_time);
+ value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
+ writel(value, ®s->lcdc_lcdcfg5);
+
+ /* Vertical & Horizontal Timing */
+ value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1);
+ value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1);
+ writel(value, ®s->lcdc_lcdcfg1);
+
+ value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ);
+ value |= LCDC_LCDCFG2_VFPW(timing->vfront_porch.typ - 1);
+ writel(value, ®s->lcdc_lcdcfg2);
+
+ value = LCDC_LCDCFG3_HBPW(timing->hback_porch.typ - 1);
+ value |= LCDC_LCDCFG3_HFPW(timing->hfront_porch.typ - 1);
+ writel(value, ®s->lcdc_lcdcfg3);
+
+ /* Display size */
+ value = LCDC_LCDCFG4_RPF(timing->vactive.typ - 1);
+ value |= LCDC_LCDCFG4_PPL(timing->hactive.typ - 1);
+ writel(value, ®s->lcdc_lcdcfg4);
+
+ writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
+ ®s->lcdc_basecfg0);
+
+ switch (VNBITS(priv->vl_bpix)) {
+ case 16:
+ writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
+ ®s->lcdc_basecfg1);
+ break;
+ case 32:
+ writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
+ ®s->lcdc_basecfg1);
+ break;
+ default:
+ BUG();
+ break;
+ }
+
+ writel(LCDC_BASECFG2_XSTRIDE(0), ®s->lcdc_basecfg2);
+ writel(0, ®s->lcdc_basecfg3);
+ writel(LCDC_BASECFG4_DMA, ®s->lcdc_basecfg4);
+
+ /* Disable all interrupts */
+ writel(~0UL, ®s->lcdc_lcdidr);
+ writel(~0UL, ®s->lcdc_baseidr);
+
+ /* Setup the DMA descriptor, this descriptor will loop to itself */
+ desc = (struct lcd_dma_desc *)(uc_plat->base - 16);
+
+ desc->address = (u32)uc_plat->base;
+
+ /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
+ desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
+ | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
+ desc->next = (u32)desc;
+
+ /* Flush the DMA descriptor if we enabled dcache */
+ flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
+
+ writel(desc->address, ®s->lcdc_baseaddr);
+ writel(desc->control, ®s->lcdc_basectrl);
+ writel(desc->next, ®s->lcdc_basenext);
+ writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
+ ®s->lcdc_basecher);
+
+ /* Enable LCD */
+ value = readl(®s->lcdc_lcden);
+ writel(value | LCDC_LCDEN_CLKEN, ®s->lcdc_lcden);
+ ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
+ true, 1000, false);
+ if (ret)
+ printf("%s: %d: Timeout!\n", __func__, __LINE__);
+ value = readl(®s->lcdc_lcden);
+ writel(value | LCDC_LCDEN_SYNCEN, ®s->lcdc_lcden);
+ ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
+ true, 1000, false);
+ if (ret)
+ printf("%s: %d: Timeout!\n", __func__, __LINE__);
+ value = readl(®s->lcdc_lcden);
+ writel(value | LCDC_LCDEN_DISPEN, ®s->lcdc_lcden);
+ ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
+ true, 1000, false);
+ if (ret)
+ printf("%s: %d: Timeout!\n", __func__, __LINE__);
+ value = readl(®s->lcdc_lcden);
+ writel(value | LCDC_LCDEN_PWMEN, ®s->lcdc_lcden);
+ ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
+ true, 1000, false);
+ if (ret)
+ printf("%s: %d: Timeout!\n", __func__, __LINE__);
+}
+
+static int atmel_hlcdc_probe(struct udevice *dev)
+{
+ struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = at91_hlcdc_enable_clk(dev);
+ if (ret)
+ return ret;
+
+ atmel_hlcdc_init(dev);
+
+ uc_priv->xsize = priv->timing.hactive.typ;
+ uc_priv->ysize = priv->timing.vactive.typ;
+ uc_priv->bpix = priv->vl_bpix;
+
+ /* Enable flushing if we enabled dcache */
+ video_set_flush_dcache(dev, true);
+
+ return 0;
+}
+
+static int atmel_hlcdc_ofdata_to_platdata(struct udevice *dev)
+{
+ struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
+
+ priv->regs = (struct atmel_hlcd_regs *)dev_get_addr(dev);
+ if (!priv->regs) {
+ debug("%s: No display controller address\n", __func__);
+ return -EINVAL;
+ }
+
+ if (fdtdec_decode_display_timing(blob, dev->of_offset,
+ 0, &priv->timing)) {
+ debug("%s: Failed to decode display timing\n", __func__);
+ return -EINVAL;
+ }
+
+ if (priv->timing.hactive.typ > LCD_MAX_WIDTH)
+ priv->timing.hactive.typ = LCD_MAX_WIDTH;
+
+ if (priv->timing.vactive.typ > LCD_MAX_HEIGHT)
+ priv->timing.vactive.typ = LCD_MAX_HEIGHT;
+
+ priv->vl_bpix = fdtdec_get_int(blob, node, "atmel,vl-bpix", 0);
+ if (!priv->vl_bpix) {
+ debug("%s: Failed to get bits per pixel\n", __func__);
+ return -EINVAL;
+ }
+
+ priv->output_mode = fdtdec_get_int(blob, node, "atmel,output-mode", 24);
+ priv->guard_time = fdtdec_get_int(blob, node, "atmel,guard-time", 1);
+
+ return 0;
+}
+
+static int atmel_hlcdc_bind(struct udevice *dev)
+{
+ struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+
+ uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
+ (1 << LCD_MAX_LOG2_BPP) / 8;
+
+ debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
+
+ return 0;
+}
+
+static const struct udevice_id atmel_hlcdc_ids[] = {
+ { .compatible = "atmel,sama5d2-hlcdc" },
+ { .compatible = "atmel,at91sam9x5-hlcdc" },
+ { }
+};
+
+U_BOOT_DRIVER(atmel_hlcdfb) = {
+ .name = "atmel_hlcdfb",
+ .id = UCLASS_VIDEO,
+ .of_match = atmel_hlcdc_ids,
+ .bind = atmel_hlcdc_bind,
+ .probe = atmel_hlcdc_probe,
+ .ofdata_to_platdata = atmel_hlcdc_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct atmel_hlcdc_priv),
+};
+
+#endif
{
struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent);
void *line;
- int pixels = VIDEO_FONT_HEIGHT * vid_priv->line_length;
+ int pixels = VIDEO_FONT_HEIGHT * vid_priv->xsize;
int i;
line = vid_priv->fb + row * VIDEO_FONT_HEIGHT * vid_priv->line_length;
#include <asm/io.h>
#include <common.h>
+#include <fdt_support.h>
#include <fsl_dcu_fb.h>
#include <linux/fb.h>
#include <malloc.h>
#define DCU_VSYN_PARA_BP(x) ((x) << 22)
#define DCU_VSYN_PARA_PW(x) ((x) << 11)
#define DCU_VSYN_PARA_FP(x) (x)
-#define DCU_SYN_POL_INV_PXCK_FALL (0 << 6)
+#define DCU_SYN_POL_INV_PXCK_FALL (1 << 6)
#define DCU_SYN_POL_NEG_REMAIN (0 << 5)
#define DCU_SYN_POL_INV_VS_LOW (1 << 1)
#define DCU_SYN_POL_INV_HS_LOW (1)
#define BPP_24_RGB888 5
#define BPP_32_ARGB8888 6
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* This setting is used for the TWR_LCD_RGB card
*/
/*
* This setting is used for Siliconimage SiI9022A HDMI
*/
-static struct fb_videomode fsl_dcu_mode_640_480 = {
+static struct fb_videomode fsl_dcu_cea_mode_640_480 = {
.name = "640x480-60",
.refresh = 60,
.xres = 640,
.vmode = FB_VMODE_NONINTERLACED,
};
+static struct fb_videomode fsl_dcu_mode_640_480 = {
+ .name = "640x480-60",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = 25175,
+ .left_margin = 40,
+ .right_margin = 24,
+ .upper_margin = 32,
+ .lower_margin = 11,
+ .hsync_len = 96,
+ .vsync_len = 2,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_videomode fsl_dcu_mode_800_480 = {
+ .name = "800x480-60",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 33260,
+ .left_margin = 216,
+ .right_margin = 40,
+ .upper_margin = 35,
+ .lower_margin = 10,
+ .hsync_len = 128,
+ .vsync_len = 2,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_videomode fsl_dcu_mode_1024_600 = {
+ .name = "1024x600-60",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 600,
+ .pixclock = 48000,
+ .left_margin = 104,
+ .right_margin = 43,
+ .upper_margin = 24,
+ .lower_margin = 20,
+ .hsync_len = 5,
+ .vsync_len = 5,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
/*
* DCU register map
*/
dcu_write32(®s->ctrldescl[i][9], 0);
dcu_write32(®s->ctrldescl[i][10], 0);
}
-
- dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG);
}
static int layer_ctrldesc_init(int index, u32 pixel_format)
dcu_write32(®s->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0));
dcu_write32(®s->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0));
- dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG);
-
return 0;
}
struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
unsigned int div, mode;
- /* Memory allocation for framebuffer */
info.screen_size =
info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8);
- info.screen_base = (char *)memalign(ARCH_DMA_MINALIGN,
- roundup(info.screen_size, ARCH_DMA_MINALIGN));
+
+ if (info.screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) {
+ info.screen_size = 0;
+ return -ENOMEM;
+ }
+
+ /* Reserve framebuffer at the end of memory */
+ gd->fb_base = gd->bd->bi_dram[0].start +
+ gd->bd->bi_dram[0].size - info.screen_size;
+ info.screen_base = (char *)gd->fb_base;
+
memset(info.screen_base, 0, info.screen_size);
reset_total_layers();
- div = dcu_set_pixel_clock(info.var.pixclock);
- dcu_write32(®s->div_ratio, (div - 1));
dcu_write32(®s->disp_size,
DCU_DISP_SIZE_DELTA_Y(info.var.yres) |
DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0));
dcu_write32(®s->mode,
- DCU_MODE_BLEND_ITER(DCU_LAYER_MAX_NUM) |
+ DCU_MODE_BLEND_ITER(2) |
DCU_MODE_RASTER_EN);
dcu_write32(®s->threshold,
layer_ctrldesc_init(0, pixel_format);
+ div = dcu_set_pixel_clock(info.var.pixclock);
+ dcu_write32(®s->div_ratio, (div - 1));
+
+ dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG);
+
return 0;
}
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB;
+}
+
void *video_hw_init(void)
{
static GraphicDevice ctfb;
fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
break;
case RESOLUTION(640, 480):
- fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
+ if (!strncmp(options, "monitor=hdmi", 12))
+ fsl_dcu_mode_db = &fsl_dcu_cea_mode_640_480;
+ else
+ fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
+ break;
+ case RESOLUTION(800, 480):
+ fsl_dcu_mode_db = &fsl_dcu_mode_800_480;
+ break;
+ case RESOLUTION(1024, 600):
+ fsl_dcu_mode_db = &fsl_dcu_mode_1024_600;
break;
default:
printf("unsupported resolution %ux%u\n",
return &ctfb;
}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int fsl_dcu_fixedfb_setup(void *blob)
+{
+ u64 start, size;
+ int ret;
+
+ start = gd->bd->bi_dram[0].start;
+ size = gd->bd->bi_dram[0].size - info.screen_size;
+
+ /*
+ * Align size on section size (1 MiB).
+ */
+ size &= 0xfff00000;
+ ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
+ if (ret) {
+ eprintf("Cannot setup fb: Error reserving memory\n");
+ return ret;
+ }
+
+ return 0;
+}
+#endif
#define CONFIG_MXC_OCOTP
#endif
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+#define CONFIG_CMD_BMP
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_SYS_FSL_DCU_LE
+
+#define CONFIG_SYS_DCU_ADDR DCU0_BASE_ADDR
+#define DCU_LAYER_MAX_NUM 64
+#endif
+
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
"setupdate=run setsdupdate || run setusbupdate\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
+ "video-mode=dcufb:640x480-16@60,monitor=lcd\0" \
+ "splashpos=m,m\0" \
SD_BOOTCMD \
NFS_BOOTCMD \
UBI_BOOTCMD
/*
* Video
*/
-#define CONFIG_FSL_DCU_FB
-
-#ifdef CONFIG_FSL_DCU_FB
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
#define CONFIG_CMD_BMP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
/*
* Video
*/
-#define CONFIG_FSL_DCU_FB
-
-#ifdef CONFIG_FSL_DCU_FB
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
#define CONFIG_CMD_BMP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#include "at91-sama5_common.h"
-/* serial console */
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID ATMEL_ID_DBGU
-
/*
* This needs to be defined for the OHCI code to work but it is defined as
* ATMEL_ID_UHPHS in the CPU specific header files.
#define CONFIG_SYS_SDRAM_SIZE 0x10000000
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_INIT_SP_ADDR 0x310000
+#define CONFIG_SYS_INIT_SP_ADDR 0x318000
#else
#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
/* NAND flash */
#define CONFIG_CMD_UBIFS
#endif
-/* Ethernet Hardware */
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_MACB_SEARCH_PHY
-#define CONFIG_RGMII
-#define CONFIG_PHYLIB
-
-/* MMC */
-
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
-#define CONFIG_ATMEL_MCI_8BIT
-#endif
-
/* USB */
#ifdef CONFIG_CMD_USB
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x300000
-#define CONFIG_SPL_MAX_SIZE 0x10000
+#define CONFIG_SPL_MAX_SIZE 0x18000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-/* serial console */
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID ATMEL_ID_DBGU
-
/*
* This needs to be defined for the OHCI code to work but it is defined as
* ATMEL_ID_UHPHS in the CPU specific header files.
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_INIT_SP_ADDR 0x310000
+#define CONFIG_SYS_INIT_SP_ADDR 0x318000
#else
#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
/* SerialFlash */
#ifdef CONFIG_CMD_SF
-#define CONFIG_ATMEL_SPI
#define CONFIG_SF_DEFAULT_SPEED 30000000
#endif
#define CONFIG_CMD_NAND_TRIMFFS
#endif
-/* Ethernet Hardware */
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_MACB_SEARCH_PHY
-#define CONFIG_RGMII
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
-/* MMC */
-
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
-#define ATMEL_BASE_MMCI ATMEL_BASE_MCI0
-#endif
-
/* USB */
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
#endif
-/* USB device */
-#define CONFIG_USB_ETHER
-#define CONFIG_USB_ETH_RNDIS
-#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D3xEK"
-
#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
#define CONFIG_FAT_WRITE
#endif
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x300000
-#define CONFIG_SPL_MAX_SIZE 0x10000
+#define CONFIG_SPL_MAX_SIZE 0x18000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#elif CONFIG_SYS_USE_SERIALFLASH
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#endif
int fsl_dcu_init(unsigned int xres, unsigned int yres,
unsigned int pixel_format);
+int fsl_dcu_fixedfb_setup(void *blob);
/* Prototypes for external board-specific functions */
int platform_dcu_init(unsigned int xres, unsigned int yres,
#define __LED_H
/**
- * struct led_uclass_plat - Platform data the uclass stores about each device
+ * struct led_uc_plat - Platform data the uclass stores about each device
*
* @label: LED label
*/
-struct led_uclass_plat {
+struct led_uc_plat {
const char *label;
};
+/**
+ * struct led_uc_priv - Private data the uclass stores about each device
+ *
+ * @period_ms: Flash period in milliseconds
+ */
+struct led_uc_priv {
+ int period_ms;
+};
+
+enum led_state_t {
+ LEDST_OFF = 0,
+ LEDST_ON = 1,
+ LEDST_TOGGLE,
+#ifdef CONFIG_LED_BLINK
+ LEDST_BLINK,
+#endif
+
+ LEDST_COUNT,
+};
+
struct led_ops {
/**
- * set_on() - set the state of an LED
+ * set_state() - set the state of an LED
*
* @dev: LED device to change
- * @on: 1 to turn the LED on, 0 to turn it off
+ * @state: LED state to set
* @return 0 if OK, -ve on error
*/
- int (*set_on)(struct udevice *dev, int on);
+ int (*set_state)(struct udevice *dev, enum led_state_t state);
+
+ /**
+ * led_get_state() - get the state of an LED
+ *
+ * @dev: LED device to change
+ * @return LED state led_state_t, or -ve on error
+ */
+ enum led_state_t (*get_state)(struct udevice *dev);
+
+#ifdef CONFIG_LED_BLINK
+ /**
+ * led_set_period() - set the blink period of an LED
+ *
+ * Thie records the period if supported, or returns -ENOSYS if not.
+ * To start the LED blinking, use set_state().
+ *
+ * @dev: LED device to change
+ * @period_ms: LED blink period in milliseconds
+ * @return 0 if OK, -ve on error
+ */
+ int (*set_period)(struct udevice *dev, int period_ms);
+#endif
};
#define led_get_ops(dev) ((struct led_ops *)(dev)->driver->ops)
int led_get_by_label(const char *label, struct udevice **devp);
/**
- * led_set_on() - set the state of an LED
+ * led_set_state() - set the state of an LED
+ *
+ * @dev: LED device to change
+ * @state: LED state to set
+ * @return 0 if OK, -ve on error
+ */
+int led_set_state(struct udevice *dev, enum led_state_t state);
+
+/**
+ * led_get_state() - get the state of an LED
+ *
+ * @dev: LED device to change
+ * @return LED state led_state_t, or -ve on error
+ */
+enum led_state_t led_get_state(struct udevice *dev);
+
+/**
+ * led_set_period() - set the blink period of an LED
*
* @dev: LED device to change
- * @on: 1 to turn the LED on, 0 to turn it off
+ * @period_ms: LED blink period in milliseconds
* @return 0 if OK, -ve on error
*/
-int led_set_on(struct udevice *dev, int on);
+int led_set_period(struct udevice *dev, int period_ms);
#endif
CONFIG_FSL_CADMUS
CONFIG_FSL_CORENET
CONFIG_FSL_CPLD
-CONFIG_FSL_DCU_FB
CONFIG_FSL_DCU_SII9022A
CONFIG_FSL_DDR_BIST
CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
ut_assertok(uclass_get_device(UCLASS_LED, 1, &dev));
ut_assertok(uclass_get_device(UCLASS_GPIO, 1, &gpio));
ut_asserteq(0, sandbox_gpio_get_value(gpio, offset));
- led_set_on(dev, 1);
+ ut_assertok(led_set_state(dev, LEDST_ON));
ut_asserteq(1, sandbox_gpio_get_value(gpio, offset));
- led_set_on(dev, 0);
+ ut_asserteq(LEDST_ON, led_get_state(dev));
+
+ ut_assertok(led_set_state(dev, LEDST_OFF));
ut_asserteq(0, sandbox_gpio_get_value(gpio, offset));
+ ut_asserteq(LEDST_OFF, led_get_state(dev));
return 0;
}
DM_TEST(dm_test_led_gpio, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+/* Test that we can toggle LEDs */
+static int dm_test_led_toggle(struct unit_test_state *uts)
+{
+ const int offset = 1;
+ struct udevice *dev, *gpio;
+
+ /*
+ * Check that we can manipulate an LED. LED 1 is connected to GPIO
+ * bank gpio_a, offset 1.
+ */
+ ut_assertok(uclass_get_device(UCLASS_LED, 1, &dev));
+ ut_assertok(uclass_get_device(UCLASS_GPIO, 1, &gpio));
+ ut_asserteq(0, sandbox_gpio_get_value(gpio, offset));
+ ut_assertok(led_set_state(dev, LEDST_TOGGLE));
+ ut_asserteq(1, sandbox_gpio_get_value(gpio, offset));
+ ut_asserteq(LEDST_ON, led_get_state(dev));
+
+ ut_assertok(led_set_state(dev, LEDST_TOGGLE));
+ ut_asserteq(0, sandbox_gpio_get_value(gpio, offset));
+ ut_asserteq(LEDST_OFF, led_get_state(dev));
+
+ return 0;
+}
+DM_TEST(dm_test_led_toggle, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
/* Test obtaining an LED by label */
static int dm_test_led_label(struct unit_test_state *uts)
{
return 0;
}
DM_TEST(dm_test_led_label, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test LED blinking */
+#ifdef CONFIG_LED_BLINK
+static int dm_test_led_blink(struct unit_test_state *uts)
+{
+ const int offset = 1;
+ struct udevice *dev, *gpio;
+
+ /*
+ * Check that we get an error when trying to blink an LED, since it is
+ * not supported by the GPIO LED driver.
+ */
+ ut_assertok(uclass_get_device(UCLASS_LED, 1, &dev));
+ ut_assertok(uclass_get_device(UCLASS_GPIO, 1, &gpio));
+ ut_asserteq(0, sandbox_gpio_get_value(gpio, offset));
+ ut_asserteq(-ENOSYS, led_set_state(dev, LEDST_BLINK));
+ ut_asserteq(0, sandbox_gpio_get_value(gpio, offset));
+ ut_asserteq(LEDST_OFF, led_get_state(dev));
+ ut_asserteq(-ENOSYS, led_set_period(dev, 100));
+
+ return 0;
+}
+DM_TEST(dm_test_led_blink, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+#endif
projects / platform / kernel / u-boot.git / commitdiff