net: pcs: Add 10GBASE-R mode for Synopsys Designware XPCS
authorJiawen Wu <jiawenwu@trustnetic.com>
Tue, 6 Jun 2023 09:21:05 +0000 (17:21 +0800)
committerPaolo Abeni <pabeni@redhat.com>
Thu, 8 Jun 2023 11:25:10 +0000 (13:25 +0200)
Add basic support for XPCS using 10GBASE-R interface. This mode will
be extended to use interrupt, so set pcs.poll false. And avoid soft
reset so that the device using this mode is in the default configuration.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
drivers/net/pcs/pcs-xpcs.c
include/linux/pcs/pcs-xpcs.h

index 23223f0..e4e59aa 100644 (file)
@@ -64,6 +64,16 @@ static const int xpcs_xlgmii_features[] = {
        __ETHTOOL_LINK_MODE_MASK_NBITS,
 };
 
+static const int xpcs_10gbaser_features[] = {
+       ETHTOOL_LINK_MODE_Pause_BIT,
+       ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+       ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
+       ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
+       ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
+       ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
+       __ETHTOOL_LINK_MODE_MASK_NBITS,
+};
+
 static const int xpcs_sgmii_features[] = {
        ETHTOOL_LINK_MODE_Pause_BIT,
        ETHTOOL_LINK_MODE_Asym_Pause_BIT,
@@ -106,6 +116,10 @@ static const phy_interface_t xpcs_xlgmii_interfaces[] = {
        PHY_INTERFACE_MODE_XLGMII,
 };
 
+static const phy_interface_t xpcs_10gbaser_interfaces[] = {
+       PHY_INTERFACE_MODE_10GBASER,
+};
+
 static const phy_interface_t xpcs_sgmii_interfaces[] = {
        PHY_INTERFACE_MODE_SGMII,
 };
@@ -123,6 +137,7 @@ enum {
        DW_XPCS_USXGMII,
        DW_XPCS_10GKR,
        DW_XPCS_XLGMII,
+       DW_XPCS_10GBASER,
        DW_XPCS_SGMII,
        DW_XPCS_1000BASEX,
        DW_XPCS_2500BASEX,
@@ -246,6 +261,7 @@ static int xpcs_soft_reset(struct dw_xpcs *xpcs,
 
        switch (compat->an_mode) {
        case DW_AN_C73:
+       case DW_10GBASER:
                dev = MDIO_MMD_PCS;
                break;
        case DW_AN_C37_SGMII:
@@ -802,6 +818,8 @@ int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,
                return -ENODEV;
 
        switch (compat->an_mode) {
+       case DW_10GBASER:
+               break;
        case DW_AN_C73:
                if (test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, advertising)) {
                        ret = xpcs_config_aneg_c73(xpcs, compat);
@@ -998,6 +1016,9 @@ static void xpcs_get_state(struct phylink_pcs *pcs,
                return;
 
        switch (compat->an_mode) {
+       case DW_10GBASER:
+               phylink_mii_c45_pcs_get_state(xpcs->mdiodev, state);
+               break;
        case DW_AN_C73:
                ret = xpcs_get_state_c73(xpcs, state, compat);
                if (ret) {
@@ -1153,6 +1174,12 @@ static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
                .num_interfaces = ARRAY_SIZE(xpcs_xlgmii_interfaces),
                .an_mode = DW_AN_C73,
        },
+       [DW_XPCS_10GBASER] = {
+               .supported = xpcs_10gbaser_features,
+               .interface = xpcs_10gbaser_interfaces,
+               .num_interfaces = ARRAY_SIZE(xpcs_10gbaser_interfaces),
+               .an_mode = DW_10GBASER,
+       },
        [DW_XPCS_SGMII] = {
                .supported = xpcs_sgmii_features,
                .interface = xpcs_sgmii_interfaces,
@@ -1256,6 +1283,9 @@ static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev,
                }
 
                xpcs->pcs.ops = &xpcs_phylink_ops;
+               if (compat->an_mode == DW_10GBASER)
+                       return xpcs;
+
                xpcs->pcs.poll = true;
 
                ret = xpcs_soft_reset(xpcs, compat);
index 914e387..ec8175b 100644 (file)
@@ -18,6 +18,7 @@
 #define DW_AN_C37_SGMII                        2
 #define DW_2500BASEX                   3
 #define DW_AN_C37_1000BASEX            4
+#define DW_10GBASER                    5
 
 struct xpcs_id;