These boards have not been converted to generic board by the deadline.
Remove all cpu9260 and cpuat91 boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
#define MACH_TYPE_INTELMOTE2 775
#define MACH_TYPE_TRIZEPS4 776
#define MACH_TYPE_PNX4008 782
-#define MACH_TYPE_CPUAT91 787
#define MACH_TYPE_IQ81340SC 799
#define MACH_TYPE_IQ81340MC 801
#define MACH_TYPE_MICRO9 811
# define machine_is_pnx4008() (0)
#endif
-#ifdef CONFIG_MACH_CPUAT91
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CPUAT91
-# endif
-# define machine_is_cpuat91() (machine_arch_type == MACH_TYPE_CPUAT91)
-#else
-# define machine_is_cpuat91() (0)
-#endif
-
#ifdef CONFIG_MACH_IQ81340SC
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_is_omap_zoom2() (0)
#endif
-#ifdef CONFIG_MACH_CPUAT9260
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CPUAT9260
-# endif
-# define machine_is_cpuat9260() (machine_arch_type == MACH_TYPE_CPUAT9260)
-#else
-# define machine_is_cpuat9260() (0)
-#endif
-
-#ifdef CONFIG_MACH_EUKREA_CPUIMX27
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX27
-# endif
-# define machine_is_eukrea_cpuimx27() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX27)
-#else
-# define machine_is_eukrea_cpuimx27() (0)
-#endif
-
#ifdef CONFIG_MACH_ACS5K
# ifdef machine_arch_type
# undef machine_arch_type
bool "Support eb_cpux9k2"
select CPU_ARM920T
-config TARGET_CPUAT91
- bool "Support cpuat91"
- select CPU_ARM920T
-
config TARGET_AT91SAM9260EK
bool "Atmel at91sam9260 reference board"
select CPU_ARM926EJS
bool "Support otc570"
select CPU_ARM926EJS
-config TARGET_CPU9260
- bool "Support cpu9260"
- select CPU_ARM926EJS
-
config TARGET_CORVUS
bool "Support corvus"
select CPU_ARM926EJS
source "board/atmel/sama5d4_xplained/Kconfig"
source "board/atmel/sama5d4ek/Kconfig"
source "board/BuS/eb_cpux9k2/Kconfig"
-source "board/eukrea/cpuat91/Kconfig"
source "board/bluewater/snapper9260/Kconfig"
source "board/BuS/vl_ma2sc/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/esd/meesc/Kconfig"
source "board/esd/otc570/Kconfig"
-source "board/eukrea/cpu9260/Kconfig"
source "board/mini-box/picosam9g45/Kconfig"
source "board/ronetix/pm9261/Kconfig"
source "board/ronetix/pm9263/Kconfig"
+++ /dev/null
-if TARGET_CPU9260
-
-config SYS_BOARD
- default "cpu9260"
-
-config SYS_VENDOR
- default "eukrea"
-
-config SYS_CONFIG_NAME
- default "cpu9260"
-
-endif
+++ /dev/null
-CPU9260 BOARD
-M: Eric Benard <eric@eukrea.com>
-S: Maintained
-F: board/eukrea/cpu9260/
-F: include/configs/cpu9260.h
-F: configs/cpu9260_defconfig
-F: configs/cpu9260_128M_defconfig
-F: configs/cpu9260_nand_defconfig
-F: configs/cpu9260_nand_128M_defconfig
-F: configs/cpu9G20_defconfig
-F: configs/cpu9G20_128M_defconfig
-F: configs/cpu9G20_nand_defconfig
-F: configs/cpu9G20_nand_128M_defconfig
+++ /dev/null
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Stelian Pop <stelian@popies.net
-# Lead Tech Design <www.leadtechdesign.com>
-# Ilko Iliev <www.ronetix.at>
-#
-# (C) Copyright 2009
-# Eric Benard <eric@eukrea.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += cpu9260.o
-obj-y += led.o
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- * Ilko Iliev <www.ronetix.at>
- *
- * (C) Copyright 2009-2011
- * Eric Benard <eric@eukrea.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/at91sam9260.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_matrix.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/hardware.h>
-#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
-#include <net.h>
-#endif
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-#ifdef CONFIG_CMD_NAND
-static void cpu9260_nand_hw_init(void)
-{
- unsigned long csa;
- at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC;
- at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- /* Enable CS3 */
- csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
- writel(csa, &matrix->csa);
-
- /* Configure SMC CS3 for NAND/SmartMedia */
-#if defined(CONFIG_CPU9G20)
- writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
- &smc->cs[3].setup);
- writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
- AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
- &smc->cs[3].pulse);
- writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
- &smc->cs[3].cycle);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(3),
- &smc->cs[3].mode);
-#elif defined(CONFIG_CPU9260)
- writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
- &smc->cs[3].setup);
- writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
- AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
- &smc->cs[3].pulse);
- writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
- &smc->cs[3].cycle);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(2),
- &smc->cs[3].mode);
-#endif
-
- writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
-
- /* Configure RDY/BSY */
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
-
- /* Enable NandFlash */
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-}
-#endif
-
-#ifdef CONFIG_MACB
-static void cpu9260_macb_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- /* Enable clock */
- writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
-
- at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
-
- at91_phy_reset();
-
- at91_macb_hw_init();
-}
-#endif
-
-int board_early_init_f(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- writel((1 << ATMEL_ID_PIOA) |
- (1 << ATMEL_ID_PIOB) |
- (1 << ATMEL_ID_PIOC),
- &pmc->pcer);
-
- at91_seriald_hw_init();
-
- return 0;
-}
-
-
-int board_init(void)
-{
- /* arch number of the board */
-#if defined(CONFIG_CPU9G20)
- gd->bd->bi_arch_number = MACH_TYPE_CPUAT9G20;
-#elif defined(CONFIG_CPU9260)
- gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260;
-#endif
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifdef CONFIG_CMD_NAND
- cpu9260_nand_hw_init();
-#endif
-#ifdef CONFIG_MACB
- cpu9260_macb_hw_init();
-#endif
-#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
- status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
-#endif
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0);
-#endif
- return rc;
-}
+++ /dev/null
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- * (C) Copyright 2009
- * Eric Benard <eric@eukrea.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <status_led.h>
-#include <asm/arch/at91sam9260.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/io.h>
-
-static unsigned int saved_state[4] = {STATUS_LED_OFF, STATUS_LED_OFF,
- STATUS_LED_OFF, STATUS_LED_OFF};
-
-void coloured_LED_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- /* Enable clock */
- writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
-
- at91_set_pio_output(CONFIG_RED_LED, 1);
- at91_set_pio_output(CONFIG_GREEN_LED, 1);
- at91_set_pio_output(CONFIG_YELLOW_LED, 1);
- at91_set_pio_output(CONFIG_BLUE_LED, 1);
-
- at91_set_pio_value(CONFIG_RED_LED, 1);
- at91_set_pio_value(CONFIG_GREEN_LED, 1);
- at91_set_pio_value(CONFIG_YELLOW_LED, 1);
- at91_set_pio_value(CONFIG_BLUE_LED, 1);
-}
-
-void red_led_off(void)
-{
- at91_set_pio_value(CONFIG_RED_LED, 1);
- saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
-}
-
-void green_led_off(void)
-{
- at91_set_pio_value(CONFIG_GREEN_LED, 1);
- saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF;
-}
-
-void yellow_led_off(void)
-{
- at91_set_pio_value(CONFIG_YELLOW_LED, 1);
- saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF;
-}
-
-void blue_led_off(void)
-{
- at91_set_pio_value(CONFIG_BLUE_LED, 1);
- saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF;
-}
-
-void red_led_on(void)
-{
- at91_set_pio_value(CONFIG_RED_LED, 0);
- saved_state[STATUS_LED_RED] = STATUS_LED_ON;
-}
-
-void green_led_on(void)
-{
- at91_set_pio_value(CONFIG_GREEN_LED, 0);
- saved_state[STATUS_LED_GREEN] = STATUS_LED_ON;
-}
-
-void yellow_led_on(void)
-{
- at91_set_pio_value(CONFIG_YELLOW_LED, 0);
- saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON;
-}
-
-void blue_led_on(void)
-{
- at91_set_pio_value(CONFIG_BLUE_LED, 0);
- saved_state[STATUS_LED_BLUE] = STATUS_LED_ON;
-}
-
-void __led_init(led_id_t mask, int state)
-{
- __led_set(mask, state);
-}
-
-void __led_toggle(led_id_t mask)
-{
- if (STATUS_LED_BLUE == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE])
- blue_led_off();
- else
- blue_led_on();
- } else if (STATUS_LED_RED == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
- red_led_off();
- else
- red_led_on();
- } else if (STATUS_LED_GREEN == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
- green_led_off();
- else
- green_led_on();
- } else if (STATUS_LED_YELLOW == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_YELLOW])
- yellow_led_off();
- else
- yellow_led_on();
- }
-}
-
-void __led_set(led_id_t mask, int state)
-{
- if (STATUS_LED_BLUE == mask) {
- if (STATUS_LED_ON == state)
- blue_led_on();
- else
- blue_led_off();
- } else if (STATUS_LED_RED == mask) {
- if (STATUS_LED_ON == state)
- red_led_on();
- else
- red_led_off();
- } else if (STATUS_LED_GREEN == mask) {
- if (STATUS_LED_ON == state)
- green_led_on();
- else
- green_led_off();
- } else if (STATUS_LED_YELLOW == mask) {
- if (STATUS_LED_ON == state)
- yellow_led_on();
- else
- yellow_led_off();
- }
-}
+++ /dev/null
-if TARGET_CPUAT91
-
-config SYS_BOARD
- default "cpuat91"
-
-config SYS_VENDOR
- default "eukrea"
-
-config SYS_CONFIG_NAME
- default "cpuat91"
-
-endif
+++ /dev/null
-CPUAT91 BOARD
-M: Eric Benard <eric@eukrea.com>
-S: Maintained
-F: board/eukrea/cpuat91/
-F: include/configs/cpuat91.h
-F: configs/cpuat91_defconfig
-F: configs/cpuat91_ram_defconfig
+++ /dev/null
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de. <http://lists.denx.de/mailman/listinfo/u-boot>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := cpuat91.o
+++ /dev/null
-/*
- * (C) Copyright 2006-2010 Eukrea Electromatique <www.eukrea.com>
- * Eric Benard <eric@eukrea.com>
- * based on at91rm9200dk.c which is :
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init(void)
-{
- /* arch number of CPUAT91-Board */
- gd->bd->bi_arch_number = MACH_TYPE_CPUAT91;
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- at91_seriald_hw_init();
- return 0;
-}
-
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_AT91EMAC
-int board_eth_init(bd_t *bis)
-{
- return at91emac_register(bis, (u32) ATMEL_BASE_EMAC);
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_SOFT
-void i2c_init_board(void)
-{
- u32 pin;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-
- writel(1 << AT91_ID_PIOA, &pmc->pcer);
- pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
- writel(pin, &pio->pioa.idr);
- writel(pin, &pio->pioa.pudr);
- writel(pin, &pio->pioa.per);
- writel(pin, &pio->pioa.oer);
- writel(pin, &pio->pioa.sodr);
-}
-#endif
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9260,CPU9260_128M"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9260=> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9260"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9260=> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9260,CPU9260_128M,NANDBOOT"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9260=> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9260,NANDBOOT"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9260=> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,CPU9G20_128M"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9G20=> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9G20"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9G20=> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,CPU9G20_128M,NANDBOOT"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9G20=> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,NANDBOOT"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9G20=> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPUAT91=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="CPUAT91=> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPUAT91=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- * Ilko Iliev <www.ronetix.at>
- *
- * (C) Copyright 2009
- * Eric Benard <eric@eukrea.com>
- *
- * Configuration settings for the Eukrea CPU9260 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* to be removed once maemory-map.h is fixed */
-#define AT91_BASE_SYS 0xffffe800
-#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_AT91SAM9G20
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_AT91SAM9260
-#else
-#error "Unknown board"
-#endif
-
-#include <asm/arch/hardware.h>
-
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#if defined(CONFIG_NANDBOOT)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_TEXT_BASE 0x23f00000
-#else
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-#endif
-
-/* clocks */
-#if defined(CONFIG_CPU9G20)
-#define MASTER_PLL_DIV 0x01
-#define MASTER_PLL_MUL 0x2B
-#elif defined(CONFIG_CPU9260)
-#define MASTER_PLL_DIV 0x09
-#define MASTER_PLL_MUL 0x61
-#endif
-
-/* CKGR_MOR - enable main osc. */
-#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOSCEN | \
- (255 << 8)) /* Main Oscillator Start-up Time */
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- AT91_PMC_OUT | \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
-#endif
-
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_6 | \
- AT91_PMC_PDIV_2)
-#define CONFIG_SYS_MCKR2_VAL \
- CONFIG_SYS_MCKR1_VAL
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-#endif
-
-/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
-/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
-
-/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
-#define CONFIG_SYS_MATRIX_EBICSA_VAL \
- (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \
- AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V)
-
-/* SDRAM */
-/* SDRAMC_MR Mode register */
-#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
-/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x287
-/* SDRAMC_CR - Configuration register*/
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_SDRC_CR_VAL_64MB \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_2 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* Write Recovery Delay */ \
- (9 << 12) | /* Row Cycle Delay */ \
- (3 << 16) | /* Row Precharge Delay */ \
- (3 << 20) | /* Row to Column Delay */ \
- (6 << 24) | /* Active to Precharge Delay */ \
- (10 << 28)) /* Exit Self Refresh to Active Delay */
-
-#define CONFIG_SYS_SDRC_CR_VAL_128MB \
- (AT91_SDRAMC_NC_10 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_2 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* Write Recovery Delay */ \
- (9 << 12) | /* Row Cycle Delay */ \
- (3 << 16) | /* Row Precharge Delay */ \
- (3 << 20) | /* Row to Column Delay */ \
- (6 << 24) | /* Active to Precharge Delay */ \
- (10 << 28)) /* Exit Self Refresh to Active Delay */
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_SDRC_CR_VAL_64MB \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_2 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* Write Recovery Delay */ \
- (7 << 12) | /* Row Cycle Delay */ \
- (2 << 16) | /* Row Precharge Delay */ \
- (2 << 20) | /* Row to Column Delay */ \
- (5 << 24) | /* Active to Precharge Delay */ \
- (8 << 28)) /* Exit Self Refresh to Active Delay */
-
-#define CONFIG_SYS_SDRC_CR_VAL_128MB \
- (AT91_SDRAMC_NC_10 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_2 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* Write Recovery Delay */ \
- (7 << 12) | /* Row Cycle Delay */ \
- (2 << 16) | /* Row Precharge Delay */ \
- (2 << 20) | /* Row to Column Delay */ \
- (5 << 24) | /* Active to Precharge Delay */ \
- (8 << 28)) /* Exit Self Refresh to Active Delay */
-#endif
-
-/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
-#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
-#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
-#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
-#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
-
-/* setup SMC0, CS0 (NOR Flash) - 16-bit */
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_SMC0_SETUP0_VAL \
- (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
- AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
-#define CONFIG_SYS_SMC0_PULSE0_VAL \
- (AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) | \
- AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL \
- (AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14))
-#define CONFIG_SYS_SMC0_MODE0_VAL \
- (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
- AT91_SMC_MODE_DBW_16 | \
- AT91_SMC_MODE_TDF | \
- AT91_SMC_MODE_TDF_CYCLE(3))
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_SMC0_SETUP0_VAL \
- (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
- AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
-#define CONFIG_SYS_SMC0_PULSE0_VAL \
- (AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) | \
- AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL \
- (AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10))
-#define CONFIG_SYS_SMC0_MODE0_VAL \
- (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
- AT91_SMC_MODE_DBW_16 | \
- AT91_SMC_MODE_TDF | \
- AT91_SMC_MODE_TDF_CYCLE(2))
-#endif
-
-/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
- (AT91_RSTC_KEY | \
- AT91_RSTC_CR_PROCRST | \
- AT91_RSTC_MR_ERSTL(1) | \
- AT91_RSTC_MR_ERSTL(2))
-
-/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
- AT91_WDT_MR_WDV(0xfff) | \
- AT91_WDT_MR_WDDIS | \
- AT91_WDT_MR_WDD(0xfff))
-
-/*
- * Hardware drivers
- */
-#define CONFIG_AT91SAM9_WATCHDOG
-#define CONFIG_AT91_GPIO
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID ATMEL_ID_SYS
-
-#define CONFIG_BOOTDELAY 3
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MII
-
-/* SDRAM */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
-#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
-#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
-#else
-#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
-#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
-#endif
-
-/* NAND flash */
-#define CONFIG_NAND_ATMEL
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_DBW_8 1
-#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PC(13)
-#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-
-/* NOR flash */
-#if defined(CONFIG_NANDBOOT)
-#define CONFIG_SYS_NO_FLASH
-#else
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define PHYS_FLASH_1 0x10000000
-#define PHYS_FLASH_2 0x12000000
-#define CONFIG_SYS_FLASH_BANKS_LIST \
- { PHYS_FLASH_1, PHYS_FLASH_2 }
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_SECT (255+4)
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
-#endif
-
-/* Ethernet */
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_MACB_SEARCH_PHY
-#define CONFIG_AT91_WANTS_COMMON_PHY
-
-/* LEDS */
-/* Status LED */
-#define CONFIG_STATUS_LED
-#define CONFIG_BOARD_SPECIFIC_LED
-#define STATUS_LED_RED 0
-#define STATUS_LED_GREEN 1
-#define STATUS_LED_YELLOW 2
-#define STATUS_LED_BLUE 3
-/* Red */
-#define STATUS_LED_BIT STATUS_LED_RED
-#define STATUS_LED_STATE STATUS_LED_OFF
-#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-/* Green */
-#define STATUS_LED_BIT1 STATUS_LED_GREEN
-#define STATUS_LED_STATE1 STATUS_LED_OFF
-#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
-/* Yellow */
-#define STATUS_LED_BIT2 STATUS_LED_YELLOW
-#define STATUS_LED_STATE2 STATUS_LED_OFF
-#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
-/* Blue */
-#define STATUS_LED_BIT3 STATUS_LED_BLUE
-#define STATUS_LED_STATE3 STATUS_LED_ON
-#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
-/* Optional value */
-#define STATUS_LED_BOOT STATUS_LED_BIT
-
-#define CONFIG_RED_LED AT91_PIO_PORTC, 11
-#define CONFIG_GREEN_LED AT91_PIO_PORTC, 12
-#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 7
-#define CONFIG_BLUE_LED AT91_PIO_PORTC, 9
-
-/* USB */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g20"
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
-#endif
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_USB_STORAGE
-
-#define CONFIG_SYS_LOAD_ADDR 0x21000000
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END \
- (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
-
-#if defined(CONFIG_NANDBOOT)
-#define CONFIG_SYS_USE_NANDFLASH
-#undef CONFIG_SYS_USE_FLASH
-#else
-#define CONFIG_SYS_USE_FLASH
-#undef CONFIG_SYS_USE_NANDFLASH
-#endif
-
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_BASEDIR "cpu9G20"
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_BASEDIR "cpu9260"
-#endif
-
-#if defined(CONFIG_SYS_USE_FLASH)
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x40000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BOOTCOMMAND "run flashboot"
-
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
-#define MTDPARTS_DEFAULT \
- "mtdparts=physmap-flash.0:" \
- "256k(u-boot)ro," \
- "128k(u-boot-env)ro," \
- "1792k(kernel)," \
- "-(rootfs);" \
- "atmel_nand:-(nand)"
-
-#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "mtdids=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "partition=nand0,0\0" \
- "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
- "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
- "run ramargs;bootm 22000000\0" \
- "flashboot=run ramargs;bootm 0x10060000\0" \
- "basedir=" CONFIG_SYS_BASEDIR "\0" \
- "updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \
- "off 0x10000000 0x1003ffff;erase 0x10000000 " \
- "0x1003ffff;cp.b 0x24000000 0x10000000 " \
- "$(filesize)\0" \
- "updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \
- " 0x10060000 0x1021ffff;erase 0x10060000 " \
- "0x1021ffff;cp.b 0x24000000 0x10060000 " \
- "$(filesize)\0" \
- "updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \
- "protect off 0x10220000 0x13ffffff;erase " \
- "0x10220000 0x13ffffff;cp.b 0x24000000 " \
- "0x10220000 $(filesize)\0" \
- ""
-#elif defined(CONFIG_NANDBOOT)
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x60000
-#define CONFIG_ENV_OFFSET_REDUND 0x80000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BOOTCOMMAND "run flashboot"
-
-#define MTDIDS_DEFAULT "nand0=atmel_nand"
-#define MTDPARTS_DEFAULT \
- "mtdparts=atmel_nand:" \
- "128k(bootstrap)ro," \
- "256k(u-boot)ro," \
- "128k(u-boot-env)ro," \
- "128k(u-boot-env2)ro," \
- "2M(kernel)," \
- "-(rootfs)"
-
-#define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs " \
- "ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "mtdids=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "partition=nand0,5\0" \
- "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
- "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
- "run ramargs;bootm 22000000\0" \
- "flashboot=run ramargs; nand read 0x22000000 0xA0000 " \
- "0x200000; bootm 0x22000000\0" \
- "basedir=" CONFIG_SYS_BASEDIR "\0" \
- "u-boot=u-boot-eukrea-cpu9260.bin\0" \
- "kernel=uImage-eukrea-cpu9260.bin\0" \
- "rootfs=image-eukrea-cpu9260.ubi\0" \
- "updtub=tftp ${loadaddr} $(basedir)/${u-boot}; " \
- "nand erase 20000 40000; " \
- "nand write ${loadaddr} 20000 40000\0" \
- "updtui=tftp ${loadaddr} $(basedir)/${kernel}; " \
- "nand erase a0000 200000; " \
- "nand write ${loadaddr} a0000 200000\0" \
- "updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; " \
- "nand erase 2a0000 fd60000; " \
- "nand write ${loadaddr} 2a0000 ${filesize}\0"
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SILENT_CONSOLE
-#define CONFIG_NETCONSOLE
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN \
- ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
- GENERATED_GBL_DATA_SIZE)
-
-#endif
+++ /dev/null
-/*
- * CPUAT91 by (C) Copyright 2006-2010 Eric Benard
- * eric@eukrea.com
- *
- * Configuration settings for the CPUAT91 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CONFIG_CPUAT91_H
-#define _CONFIG_CPUAT91_H
-
-#include <linux/sizes.h>
-
-#ifdef CONFIG_RAMBOOT
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_TEXT_BASE 0x21F00000
-#else
-#define CONFIG_BOOTDELAY 1
-#define CONFIG_SYS_TEXT_BASE 0
-#endif
-
-#define AT91C_XTAL_CLOCK 18432000
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
-#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
-#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
-
-#define CONFIG_AT91RM9200
-#define CONFIG_CPUAT91
-#define USE_920T_MMU
-
-#include <asm/hardware.h> /* needed for port definitions */
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_USE_MAIN_OSCILLATOR
-/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
-#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
-#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
-
-/* clocks */
-#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
-#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz for USB */
-#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock */
-
-/* sdram */
-#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as D16/D31 */
-#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
-#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
-#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
-#define CONFIG_SYS_SDRC_CR_VAL 0x2188C155 /* set up the SDRAM */
-#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */
-#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */
-#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */
-#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
-#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
-#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
-#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
-#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID 0/* ignored in arm */
-
-#undef CONFIG_HARD_I2C
-#define AT91_PIN_SDA (1<<25)
-#define AT91_PIN_SCL (1<<26)
-
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
-
-#define I2C_INIT i2c_init_board();
-#define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr);
-#define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder);
-#define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0)
-#define I2C_SDA(bit) \
- if (bit) \
- writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \
- else \
- writel(AT91_PMX_AA_TWD, &pio->pioa.codr);
-#define I2C_SCL(bit) \
- if (bit) \
- writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \
- else \
- writel(AT91_PMX_AA_TWCK, &pio->pioa.codr);
-
-#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_CACHE
-#undef CONFIG_CMD_USB
-#undef CONFIG_CMD_DHCP
-
-#ifdef CONFIG_SYS_I2C_SOFT
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#endif
-
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END \
- (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
-
-#define CONFIG_DRIVER_AT91EMAC
-#define CONFIG_SYS_RX_ETH_BUFFER 16
-#define CONFIG_RMII
-#define CONFIG_MII
-#define CONFIG_DRIVER_AT91EMAC_PHYADDR 1
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_KS8721_PHY
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_PROTECTION
-#define PHYS_FLASH_1 0x10000000
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_SECT 128
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
-#define PHYS_FLASH_SIZE (16 * 1024 * 1024)
-#define CONFIG_SYS_FLASH_BANKS_LIST \
- { PHYS_FLASH_1 }
-
-#if defined(CONFIG_CMD_USB)
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_AT91C_PQFP_UHPBU
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#endif
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 128 * 1024)
-#define CONFIG_ENV_SIZE (128 * 1024)
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-
-#define CONFIG_SYS_LOAD_ADDR 0x21000000
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 32
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_CMDLINE_EDITING
-
-#define CONFIG_SYS_MALLOC_LEN \
- ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 4 * 1024)
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
- GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_DEVICE_NULLDEV
-#define CONFIG_SILENT_CONSOLE
-
-#define CONFIG_VERSION_VARIABLE
-
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
-#define MTDPARTS_DEFAULT \
- "mtdparts=physmap-flash.0:" \
- "128k(u-boot)ro," \
- "128k(u-boot-env)," \
- "1792k(kernel)," \
- "-(rootfs)"
-
-#define CONFIG_BOOTARGS \
- "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,115200"
-
-#define CONFIG_BOOTCOMMAND "run flashboot"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "mtdid=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "flub=tftp 21000000 cpuat91/u-boot.bin; protect off 10000000 " \
- "1001FFFF; erase 10000000 1001FFFF; cp.b 21000000 " \
- "10000000 ${filesize}\0" \
- "flui=tftp 21000000 cpuat91/uImage; protect off 10040000 " \
- "1019ffff; erase 10040000 101fffff; cp.b 21000000 " \
- "10040000 ${filesize}\0" \
- "flrfs=tftp 21000000 cpuat91/rootfs.jffs2; protect off " \
- "10200000 10ffffff; erase 10200000 10ffffff; cp.b " \
- "21000000 10200000 ${filesize}\0" \
- "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
- "flashboot=run ramargs;bootm 10040000\0" \
- "netboot=run ramargs;tftpboot 21000000 cpuat91/uImage;" \
- "bootm 21000000\0"
-#endif /* _CONFIG_CPUAT91_H */
projects / platform / kernel / u-boot.git / commitdiff