soc: qcom: llcc: Move llcc configuration to its own function

Cleanup qcom_llcc_cfg_program() by moving llcc configuration
to a separate function of its own. Also correct misspelled
'instance' caught by checkpatch.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/51f9ad67333eedf326212dd1b040aade6978e5b1.1600151951.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 70fbe70c6213c7ae65ce34b4528da08f012c5388..95dad1c10198a7db49993fe332f8446248ba1ea2 100644 (file)
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -318,62 +318,73 @@ size_t llcc_get_slice_size(struct llcc_slice_desc *desc)
 }
 EXPORT_SYMBOL_GPL(llcc_get_slice_size);
 
-static int qcom_llcc_cfg_program(struct platform_device *pdev)
+static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config)
 {
-       int i;
+       int ret;
        u32 attr1_cfg;
        u32 attr0_cfg;
        u32 attr1_val;
        u32 attr0_val;
        u32 max_cap_cacheline;
+       struct llcc_slice_desc desc;
+
+       attr1_val = config->cache_mode;
+       attr1_val |= config->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT;
+       attr1_val |= config->fixed_size << ATTR1_FIXED_SIZE_SHIFT;
+       attr1_val |= config->priority << ATTR1_PRIORITY_SHIFT;
+
+       max_cap_cacheline = MAX_CAP_TO_BYTES(config->max_cap);
+
+       /*
+        * LLCC instances can vary for each target.
+        * The SW writes to broadcast register which gets propagated
+        * to each llcc instance (llcc0,.. llccN).
+        * Since the size of the memory is divided equally amongst the
+        * llcc instances, we need to configure the max cap accordingly.
+        */
+       max_cap_cacheline = max_cap_cacheline / drv_data->num_banks;
+       max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;
+       attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
+
+       attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id);
+
+       ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val);
+       if (ret)
+               return ret;
+
+       attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK;
+       attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
+
+       attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id);
+
+       ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val);
+       if (ret)
+               return ret;
+
+       if (config->activate_on_init) {
+               desc.slice_id = config->slice_id;
+               ret = llcc_slice_activate(&desc);
+       }
+
+       return ret;
+}
+
+static int qcom_llcc_cfg_program(struct platform_device *pdev)
+{
+       int i;
        u32 sz;
        int ret = 0;
        const struct llcc_slice_config *llcc_table;
-       struct llcc_slice_desc desc;
 
        sz = drv_data->cfg_size;
        llcc_table = drv_data->cfg;
 
        for (i = 0; i < sz; i++) {
-               attr1_cfg = LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id);
-               attr0_cfg = LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id);
-
-               attr1_val = llcc_table[i].cache_mode;
-               attr1_val |= llcc_table[i].probe_target_ways <<
-                               ATTR1_PROBE_TARGET_WAYS_SHIFT;
-               attr1_val |= llcc_table[i].fixed_size <<
-                               ATTR1_FIXED_SIZE_SHIFT;
-               attr1_val |= llcc_table[i].priority <<
-                               ATTR1_PRIORITY_SHIFT;
-
-               max_cap_cacheline = MAX_CAP_TO_BYTES(llcc_table[i].max_cap);
-
-               /* LLCC instances can vary for each target.
-                * The SW writes to broadcast register which gets propagated
-                * to each llcc instace (llcc0,.. llccN).
-                * Since the size of the memory is divided equally amongst the
-                * llcc instances, we need to configure the max cap accordingly.
-                */
-               max_cap_cacheline = max_cap_cacheline / drv_data->num_banks;
-               max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;
-               attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
-
-               attr0_val = llcc_table[i].res_ways & ATTR0_RES_WAYS_MASK;
-               attr0_val |= llcc_table[i].bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
-
-               ret = regmap_write(drv_data->bcast_regmap, attr1_cfg,
-                                       attr1_val);
+               ret = _qcom_llcc_cfg_program(&llcc_table[i]);
                if (ret)
                        return ret;
-               ret = regmap_write(drv_data->bcast_regmap, attr0_cfg,
-                                       attr0_val);
-               if (ret)
-                       return ret;
-               if (llcc_table[i].activate_on_init) {
-                       desc.slice_id = llcc_table[i].slice_id;
-                       ret = llcc_slice_activate(&desc);
-               }
        }
+
        return ret;
 }