drm/nouveau/flcn: reset sec2/gsp falcons harder
authorBen Skeggs <bskeggs@redhat.com>
Tue, 14 Jan 2020 20:34:22 +0000 (06:34 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Wed, 15 Jan 2020 00:50:28 +0000 (10:50 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h
drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c

index 2bfa9ff1170b70a4b57aaf3e24add30538370547..269814e06e93189ede5d4dfe06857477f597147b 100644 (file)
@@ -19,4 +19,5 @@ int nvkm_falcon_v1_enable(struct nvkm_falcon *);
 void nvkm_falcon_v1_disable(struct nvkm_falcon *);
 
 void gp102_sec2_flcn_bind_context(struct nvkm_falcon *, struct nvkm_memory *);
+int gp102_sec2_flcn_enable(struct nvkm_falcon *);
 #endif
index 46b2424e30f0d76ee471fa6cc471e2a8e9c6360a..27c1f868552cdb4380d0904cfda06eab792c725c 100644 (file)
@@ -92,6 +92,7 @@ struct nvkm_falcon_func {
        void (*start)(struct nvkm_falcon *);
        int (*enable)(struct nvkm_falcon *falcon);
        void (*disable)(struct nvkm_falcon *falcon);
+       int (*reset)(struct nvkm_falcon *);
 
        struct {
                u32 head;
index 0f6e8d002eea1267a95f659a83f7e22577ce3d03..9a5bae1a03cdb1862f030b50ae70169329c92739 100644 (file)
@@ -47,6 +47,15 @@ gp102_sec2_intr(struct nvkm_sec2 *sec2)
        }
 }
 
+int
+gp102_sec2_flcn_enable(struct nvkm_falcon *falcon)
+{
+       nvkm_falcon_mask(falcon, 0x3c0, 0x00000001, 0x00000001);
+       udelay(10);
+       nvkm_falcon_mask(falcon, 0x3c0, 0x00000001, 0x00000000);
+       return nvkm_falcon_v1_enable(falcon);
+}
+
 void
 gp102_sec2_flcn_bind_context(struct nvkm_falcon *falcon,
                             struct nvkm_memory *ctx)
@@ -99,7 +108,7 @@ gp102_sec2_flcn = {
        .clear_interrupt = nvkm_falcon_v1_clear_interrupt,
        .set_start_addr = nvkm_falcon_v1_set_start_addr,
        .start = nvkm_falcon_v1_start,
-       .enable = nvkm_falcon_v1_enable,
+       .enable = gp102_sec2_flcn_enable,
        .disable = nvkm_falcon_v1_disable,
        .cmdq = { 0xa00, 0xa04, 8 },
        .msgq = { 0xa30, 0xa34, 8 },
index 36e640d3e9c3601fbf06cec3c942547265fad3e1..2114f9b00a28f0718448c0370fa8b9fe18b825ba 100644 (file)
@@ -32,7 +32,7 @@ gv100_gsp_flcn = {
        .clear_interrupt = nvkm_falcon_v1_clear_interrupt,
        .set_start_addr = nvkm_falcon_v1_set_start_addr,
        .start = nvkm_falcon_v1_start,
-       .enable = nvkm_falcon_v1_enable,
+       .enable = gp102_sec2_flcn_enable,
        .disable = nvkm_falcon_v1_disable,
 };