Forgot to add files to zylonite branch.
authorMarkus Klotzbücher <Markus Klotzbümk@pollux.(none)>
Tue, 7 Feb 2006 19:48:45 +0000 (20:48 +0100)
committerMarkus Klotzbücher <mk@pollux.(none)>
Tue, 7 Feb 2006 19:48:45 +0000 (20:48 +0100)
board/zylonite/Makefile [new file with mode: 0644]
board/zylonite/config.mk [new file with mode: 0644]
board/zylonite/flash.c [new file with mode: 0644]
board/zylonite/lowlevel_init.S [new file with mode: 0644]
board/zylonite/u-boot.lds [new file with mode: 0644]
board/zylonite/zylonite.c [new file with mode: 0644]
include/configs/zylonite.h [new file with mode: 0644]

diff --git a/board/zylonite/Makefile b/board/zylonite/Makefile
new file mode 100644 (file)
index 0000000..999647f
--- /dev/null
@@ -0,0 +1,48 @@
+
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   := zylonite.o flash.o
+SOBJS  := lowlevel_init.o
+
+$(LIB):        $(OBJS) $(SOBJS)
+       $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/zylonite/config.mk b/board/zylonite/config.mk
new file mode 100644 (file)
index 0000000..09b0f71
--- /dev/null
@@ -0,0 +1,4 @@
+#TEXT_BASE = 0x0
+#TEXT_BASE = 0xa1700000
+#TEXT_BASE = 0xa3080000
+TEXT_BASE = 0xa3008000
diff --git a/board/zylonite/flash.c b/board/zylonite/flash.c
new file mode 100644 (file)
index 0000000..ba82892
--- /dev/null
@@ -0,0 +1,431 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];  /* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH               ushort
+#define FLASH_PORT_WIDTHV              vu_short
+#define SWAP(x)               __swab16(x)
+#else
+#define FLASH_PORT_WIDTH               ulong
+#define FLASH_PORT_WIDTHV              vu_long
+#define SWAP(x)               __swab32(x)
+#endif
+
+#define FPW       FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+       int i;
+       ulong size = 0;
+
+       for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+               switch (i) {
+               case 0:
+                       flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+                       flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+                       break;
+               case 1:
+                       flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+                       flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+                       break;
+               default:
+                       panic ("configured too many flash banks!\n");
+                       break;
+               }
+               size += flash_info[i].size;
+       }
+
+       /* Protect monitor and environment sectors
+        */
+       flash_protect ( FLAG_PROTECT_SET,
+                       CFG_FLASH_BASE,
+                       CFG_FLASH_BASE + monitor_flash_len - 1,
+                       &flash_info[0] );
+
+       flash_protect ( FLAG_PROTECT_SET,
+                       CFG_ENV_ADDR,
+                       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+
+       return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+       int i;
+
+       if (info->flash_id == FLASH_UNKNOWN) {
+               return;
+       }
+
+       if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+               for (i = 0; i < info->sector_count; i++) {
+                       info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+                       info->protect[i] = 0;
+               }
+       }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+       int i;
+
+       if (info->flash_id == FLASH_UNKNOWN) {
+               printf ("missing or unknown FLASH type\n");
+               return;
+       }
+
+       switch (info->flash_id & FLASH_VENDMASK) {
+       case FLASH_MAN_INTEL:
+               printf ("INTEL ");
+               break;
+       default:
+               printf ("Unknown Vendor ");
+               break;
+       }
+
+       switch (info->flash_id & FLASH_TYPEMASK) {
+       case FLASH_28F128J3A:
+               printf ("28F128J3A\n");
+               break;
+       default:
+               printf ("Unknown Chip Type\n");
+               break;
+       }
+
+       printf ("  Size: %ld MB in %d Sectors\n",
+                       info->size >> 20, info->sector_count);
+
+       printf ("  Sector Start Addresses:");
+       for (i = 0; i < info->sector_count; ++i) {
+               if ((i % 5) == 0)
+                       printf ("\n   ");
+               printf (" %08lX%s",
+                       info->start[i],
+                       info->protect[i] ? " (RO)" : "     ");
+       }
+       printf ("\n");
+       return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+       volatile FPW value;
+
+       /* Write auto select command: read Manufacturer ID */
+       addr[0x5555] = (FPW) 0x00AA00AA;
+       addr[0x2AAA] = (FPW) 0x00550055;
+       addr[0x5555] = (FPW) 0x00900090;
+
+       mb ();
+       value = addr[0];
+
+       switch (value) {
+
+       case (FPW) INTEL_MANUFACT:
+               info->flash_id = FLASH_MAN_INTEL;
+               break;
+
+       default:
+               info->flash_id = FLASH_UNKNOWN;
+               info->sector_count = 0;
+               info->size = 0;
+               addr[0] = (FPW) 0x00FF00FF;     /* restore read mode */
+               return (0);                     /* no or unknown flash  */
+       }
+
+       mb ();
+       value = addr[1];                        /* device ID        */
+
+       switch (value) {
+
+       case (FPW) INTEL_ID_28F128J3A:
+               info->flash_id += FLASH_28F128J3A;
+               info->sector_count = 128;
+               info->size = 0x02000000;
+               break;                          /* => 16 MB     */
+
+       default:
+               info->flash_id = FLASH_UNKNOWN;
+               break;
+       }
+
+       if (info->sector_count > CFG_MAX_FLASH_SECT) {
+               printf ("** ERROR: sector count %d > max (%d) **\n",
+                       info->sector_count, CFG_MAX_FLASH_SECT);
+               info->sector_count = CFG_MAX_FLASH_SECT;
+       }
+
+       addr[0] = (FPW) 0x00FF00FF;             /* restore read mode */
+
+       return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+       int flag, prot, sect;
+       ulong type, start, last;
+       int rcode = 0;
+
+       if ((s_first < 0) || (s_first > s_last)) {
+               if (info->flash_id == FLASH_UNKNOWN) {
+                       printf ("- missing\n");
+               } else {
+                       printf ("- no sectors to erase\n");
+               }
+               return 1;
+       }
+
+       type = (info->flash_id & FLASH_VENDMASK);
+       if ((type != FLASH_MAN_INTEL)) {
+               printf ("Can't erase unknown flash type %08lx - aborted\n",
+                       info->flash_id);
+               return 1;
+       }
+
+       prot = 0;
+       for (sect = s_first; sect <= s_last; ++sect) {
+               if (info->protect[sect]) {
+                       prot++;
+               }
+       }
+
+       if (prot) {
+               printf ("- Warning: %d protected sectors will not be erased!\n",
+                       prot);
+       } else {
+               printf ("\n");
+       }
+
+       start = get_timer (0);
+       last = start;
+
+       /* Disable interrupts which might cause a timeout here */
+       flag = disable_interrupts ();
+
+       /* Start erase on unprotected sectors */
+       for (sect = s_first; sect <= s_last; sect++) {
+               if (info->protect[sect] == 0) { /* not protected */
+                       FPWV *addr = (FPWV *) (info->start[sect]);
+                       FPW status;
+
+                       printf ("Erasing sector %2d ... ", sect);
+
+                       /* arm simple, non interrupt dependent timer */
+                       reset_timer_masked ();
+
+                       *addr = (FPW) 0x00500050;       /* clear status register */
+                       *addr = (FPW) 0x00200020;       /* erase setup */
+                       *addr = (FPW) 0x00D000D0;       /* erase confirm */
+
+                       while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+                               if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+                                       printf ("Timeout\n");
+                                       *addr = (FPW) 0x00B000B0;       /* suspend erase     */
+                                       *addr = (FPW) 0x00FF00FF;       /* reset to read mode */
+                                       rcode = 1;
+                                       break;
+                               }
+                       }
+
+                       *addr = 0x00500050;     /* clear status register cmd.   */
+                       *addr = 0x00FF00FF;     /* resest to read mode          */
+
+                       printf (" done\n");
+               }
+       }
+       return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+       ulong cp, wp;
+       FPW data;
+       int count, i, l, rc, port_width;
+
+       if (info->flash_id == FLASH_UNKNOWN) {
+               return 4;
+       }
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+       wp = (addr & ~1);
+       port_width = 2;
+#else
+       wp = (addr & ~3);
+       port_width = 4;
+#endif
+
+       /*
+        * handle unaligned start bytes
+        */
+       if ((l = addr - wp) != 0) {
+               data = 0;
+               for (i = 0, cp = wp; i < l; ++i, ++cp) {
+                       data = (data << 8) | (*(uchar *) cp);
+               }
+               for (; i < port_width && cnt > 0; ++i) {
+                       data = (data << 8) | *src++;
+                       --cnt;
+                       ++cp;
+               }
+               for (; cnt == 0 && i < port_width; ++i, ++cp) {
+                       data = (data << 8) | (*(uchar *) cp);
+               }
+
+               if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+                       return (rc);
+               }
+               wp += port_width;
+       }
+
+       /*
+        * handle word aligned part
+        */
+       count = 0;
+       while (cnt >= port_width) {
+               data = 0;
+               for (i = 0; i < port_width; ++i) {
+                       data = (data << 8) | *src++;
+               }
+               if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+                       return (rc);
+               }
+               wp += port_width;
+               cnt -= port_width;
+               if (count++ > 0x800) {
+                       spin_wheel ();
+                       count = 0;
+               }
+       }
+
+       if (cnt == 0) {
+               return (0);
+       }
+
+       /*
+        * handle unaligned tail bytes
+        */
+       data = 0;
+       for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+               data = (data << 8) | *src++;
+               --cnt;
+       }
+       for (; i < port_width; ++i, ++cp) {
+               data = (data << 8) | (*(uchar *) cp);
+       }
+
+       return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+       FPWV *addr = (FPWV *) dest;
+       ulong status;
+       int flag;
+
+       /* Check if Flash is (sufficiently) erased */
+       if ((*addr & data) != data) {
+               printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+               return (2);
+       }
+       /* Disable interrupts which might cause a timeout here */
+       flag = disable_interrupts ();
+
+       *addr = (FPW) 0x00400040;       /* write setup */
+       *addr = data;
+
+       /* arm simple, non interrupt dependent timer */
+       reset_timer_masked ();
+
+       /* wait while polling the status register */
+       while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+               if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+                       *addr = (FPW) 0x00FF00FF;       /* restore read mode */
+                       return (1);
+               }
+       }
+
+       *addr = (FPW) 0x00FF00FF;       /* restore read mode */
+
+       return (0);
+}
+
+void inline spin_wheel (void)
+{
+       static int p = 0;
+       static char w[] = "\\/-";
+
+       printf ("\010%c", w[p]);
+       (++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/zylonite/lowlevel_init.S b/board/zylonite/lowlevel_init.S
new file mode 100644 (file)
index 0000000..54c2adf
--- /dev/null
@@ -0,0 +1,266 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+   .macro CPWAIT reg
+   mrc  p15,0,\reg,c2,c0,0
+   mov  \reg,\reg
+   sub  pc,pc,#4
+   .endm
+
+
+/*
+ *     Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+       /* Set up GPIO pins first ----------------------------------------- */
+       mov      r10, lr
+       
+        /*  GPIO41, 42, 43, 44, 45, 46, 47, 48 */
+       ldr             r0, =0x40E10438 @ GPIO41 FFRXD
+       ldr             r1, =0x802
+       str             r1, [r0]
+
+       ldr             r0, =0x40E1043C @ GPIO42 FFTXD
+       ldr             r1, =0x802
+       str             r1, [r0]
+
+       ldr             r0, =0x40E10440 @ GPIO43 FFCTS
+       ldr             r1, =0x802
+       str             r1, [r0]
+
+       ldr             r0, =0x40E10444 @ GPIO 44 FFDCD
+       ldr             r1, =0x802
+       str             r1, [r0]
+
+       ldr             r0, =0x40E10448 @ GPIO 45 FFDSR
+       ldr             r1, =0x802
+       str             r1, [r0]
+
+       ldr             r0, =0x40E1044C @ GPIO 46 FFRI
+       ldr             r1, =0x802
+       str             r1, [r0]
+
+       ldr             r0, =0x40E10450 @ GPIO 47 FFDTR
+       ldr             r1, =0x802
+       str             r1, [r0]
+
+       ldr             r0, =0x40E10454 @ GPIO 48
+       ldr             r1, =0x802
+       str             r1, [r0]
+
+        /* tebrandt - ASCR, clear the RDH bit */
+       ldr             r0, =ASCR
+       ldr             r1, [r0]
+       bic             r1, r1, #0x80000000
+       str             r1, [r0]
+       
+       /* ---------------------------------------------------------------- */
+       /* Enable memory interface                                          */
+       /*                                                                  */
+       /* The sequence below is based on the recommended init steps        */
+       /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+       /* Chapter 10.                                                      */
+       /* ---------------------------------------------------------------- */
+
+       /* ---------------------------------------------------------------- */
+       /* Step 1: Wait for at least 200 microsedonds to allow internal     */
+       /*         clocks to settle. Only necessary after hard reset...     */
+       /*         FIXME: can be optimized later                            */
+       /* ---------------------------------------------------------------- */
+
+       ldr r3, =OSCR                   /* reset the OS Timer Count to zero */
+       mov r2, #0
+       str r2, [r3]
+       ldr r4, =0x300                  /* really 0x2E1 is about 200usec,   */
+                                       /* so 0x300 should be plenty        */
+1:
+       ldr r2, [r3]
+       cmp r4, r2
+       bgt 1b
+
+mem_init:
+
+       /* configure the MEMCLKCFG register */
+        ldr             r1, =MEMCLKCFG
+        ldr             r2, =0x00010001
+        str             r2, [r1]             @ WRITE
+        ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
+        
+       /* set CSADRCFG[0] to data flash SRAM mode */
+       ldr             r1, =CSADRCFG0
+       ldr             r2, =0x00320809
+       str             r2, [r1]             @ WRITE
+       ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
+        
+       /* set CSADRCFG[1] to data flash SRAM mode */
+       ldr             r1, =CSADRCFG1
+       ldr             r2, =0x00320809
+       str             r2, [r1]             @ WRITE
+       ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
+        
+       /* set MSC 0 register for SRAM memory */
+        ldr             r1, =MSC0
+        ldr             r2, =0x11191119
+        str             r2, [r1]             @ WRITE
+        ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
+         
+       /* set CSADRCFG[2] to data flash SRAM mode */
+       ldr             r1, =CSADRCFG2
+       ldr             r2, =0x00320809
+       str             r2, [r1]             @ WRITE
+       ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
+        
+       /* set CSADRCFG[3] to VLIO mode */
+        ldr             r1, =CSADRCFG3
+        ldr             r2, =0x0032080B
+        str             r2, [r1]             @ WRITE
+        ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
+
+       /* set MSC 1 register for VLIO memory */
+        ldr             r1, =MSC1
+        ldr             r2, =0x123C1119
+        str             r2, [r1]             @ WRITE
+        ldr             r2, [r1]             @ DELAY UNTIL WRITTEN
+
+#if 0
+       /* This does not work in Zylonite. -SC */
+       ldr             r0, =0x15fffff0
+       ldr             r1, =0xb10b
+       str             r1, [r0]
+       str             r1, [r0, #4]
+#endif
+
+       /* Configure ACCR Register */
+       ldr             r0, =ACCR               @ ACCR
+       ldr             r1, =0x0180b108
+       str             r1, [r0]
+       ldr             r1, [r0]
+
+       /* Configure MDCNFG Register */
+       ldr             r0, =MDCNFG             @ MDCNFG
+       ldr             r1, =0x403
+       str             r1, [r0]
+       ldr             r1, [r0]
+
+       /* Perform Resistive Compensation by configuring RCOMP register */
+       ldr             r1, =RCOMP              @ RCOMP
+       ldr             r2, =0x000000ff
+       str             r2, [r1]
+       ldr             r2, [r1]
+
+       /* Configure MDMRS Register for SDCS0 */
+       ldr             r1, =MDMRS              @ MDMRS
+       ldr             r2, =0x60000023
+       ldr             r3, [r1]
+       orr             r2, r2, r3
+       str             r2, [r1]
+       ldr             r2, [r1]
+
+       /* Configure MDMRS Register for SDCS1 */
+       ldr             r1, =MDMRS              @ MDMRS
+       ldr             r2, =0xa0000023
+       ldr             r3, [r1]
+       orr             r2, r2, r3
+       str             r2, [r1]
+       ldr             r2, [r1]
+
+       /* Configure MDREFR */
+       ldr             r1, =MDREFR             @ MDREFR
+       ldr             r2, =0x00000006
+       str             r2, [r1]
+       ldr             r2, [r1]
+
+       /* Configure EMPI */
+       ldr             r1, =EMPI               @ EMPI
+       ldr             r2, =0x80000000
+       str             r2, [r1]
+       ldr             r2, [r1]
+
+       /* DDR Read-Strobe Delay Calibration */
+       /* bl   ddr_calibration */
+
+       /* Here we assume the hardware calibration alwasy be successful. -SC */
+       /* Set DMCEN bit in MDCNFG Register */
+       ldr             r0, =MDCNFG             @ MDCNFG
+       ldr             r1, [r0]
+       orr             r1, r1, #0x40000000     @ enable SDRAM for Normal Access
+       str             r1, [r0]
+
+       /* scrub/init SDRAM if enabled/present */
+       ldr     r11, =0xa0000000 //RAM_BASE     // base address of SDRAM
+       ldr     r12, =0x04000000 // size of memory to scrub
+       mov     r8,r12          // save DRAM size
+       mov     r0, #0          // scrub with 0x0000:0000
+       mov     r1, #0
+       mov     r2, #0                          
+       mov     r3, #0
+       mov     r4, #0                                  
+       mov     r5, #0
+       mov     r6, #0                                  
+       mov     r7, #0
+10:     /* fastScrubLoop */
+       subs    r12, r12, #32   // 32 bytes/line
+       stmia   r11!, {r0-r7}
+       beq     15f
+       b       10b
+
+15:
+       /* Mask all interrupts */
+       mov     r1, #0
+       mcr     p6, 0, r1, c1, c0, 0    @ ICMR
+
+       /* Disable software and data breakpoints */
+       mov     r0, #0
+       mcr     p15,0,r0,c14,c8,0  // ibcr0
+       mcr     p15,0,r0,c14,c9,0  // ibcr1
+       mcr     p15,0,r0,c14,c4,0  // dbcon
+
+       /* Enable all debug functionality */
+       mov     r0,#0x80000000
+       mcr     p14,0,r0,c10,c0,0  // dcsr
+
+
+       
+       /* We are finished with Intel's memory controller initialisation    */
+
+
+       /* ---------------------------------------------------------------- */
+       /* End lowlevel_init                                                     */
+       /* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+    mov     pc, lr
diff --git a/board/zylonite/u-boot.lds b/board/zylonite/u-boot.lds
new file mode 100644 (file)
index 0000000..f010239
--- /dev/null
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text      :
+       {
+         cpu/pxa/start.o       (.text)
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data : { *(.data) }
+
+       . = ALIGN(4);
+       .got : { *(.got) }
+
+       . = .;
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       __bss_start = .;
+       .bss : { *(.bss) }
+       _end = .;
+}
diff --git a/board/zylonite/zylonite.c b/board/zylonite/zylonite.c
new file mode 100644 (file)
index 0000000..e618ab9
--- /dev/null
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+       DECLARE_GLOBAL_DATA_PTR;
+
+       /* memory and cpu-speed are setup before relocation */
+       /* so we do _nothing_ here */
+
+       /* arch number of Lubbock-Board */
+       gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
+
+       /* adress of boot parameters */
+       gd->bd->bi_boot_params = 0xa0000100;
+
+       return 0;
+}
+
+int board_late_init(void)
+{
+       setenv("stdout", "serial");
+       setenv("stderr", "serial");
+       return 0;
+}
+
+
+int dram_init (void)
+{
+       DECLARE_GLOBAL_DATA_PTR;
+
+       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+       gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+       gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+       gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+       gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+       gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+       return 0;
+}
diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h
new file mode 100644 (file)
index 0000000..99d6a93
--- /dev/null
@@ -0,0 +1,242 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the Zylonite board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_CPU_MONAHANS    1       /* Intel Monahan CPU    */
+#define CONFIG_ZYLONITE                1       /* Zylonite board       */
+/* #define CONFIG_LCD          1 */
+#ifdef CONFIG_LCD
+#define CONFIG_SHARP_LM8V31
+#endif
+/* #define CONFIG_MMC          1 */
+#define BOARD_LATE_INIT                1
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+#undef CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN     (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE      128     /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+/* #define CONFIG_DRIVER_LAN91C96 */
+/* #define CONFIG_LAN91C96_BASE 0x0C000000 */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART         1       /* we use FFUART on LUBBOCK */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE                115200
+
+/* #define CONFIG_COMMANDS             (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */
+#define CONFIG_COMMANDS                (CONFIG_CMD_DFL & ~CFG_CMD_REISER & ~CFG_CMD_NET)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY       3
+#define CONFIG_ETHADDR         08:00:3e:26:0a:5b
+#define CONFIG_NETMASK         255.255.0.0
+#define CONFIG_IPADDR          192.168.0.21
+#define CONFIG_SERVERIP                192.168.0.250
+#define CONFIG_BOOTCOMMAND     "bootm 80000"
+#define CONFIG_BOOTARGS                "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_TIMESTAMP
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE   230400          /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX  2               /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER                1
+#define CFG_PROMPT_HUSH_PS2    "> "
+
+#define CFG_LONGHELP                           /* undef to save memory         */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT             "$ "            /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT             "=> "           /* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE             256             /* Console I/O Buffer Size      */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS            16              /* max number of command args   */
+#define CFG_BARGSIZE           CFG_CBSIZE      /* Boot Argument Buffer Size    */
+#define CFG_DEVICE_NULLDEV     1
+
+#define CFG_MEMTEST_START      0xa0400000      /* memtest works on     */
+#define CFG_MEMTEST_END                0xa0800000      /* 4 ... 8 MB in DRAM   */
+
+#undef CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR  (CFG_DRAM_BASE + 0x8000) /* default load address */
+
+#define CFG_HZ                 3686400         /* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED           0x161           /* set core clock to 400/200/100 MHz */
+
+                                               /* valid baudrates */
+#define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200 }
+
+/* #define CFG_MMC_BASE                0xF0000000 */
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE       (128*1024)      /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ   (4*1024)        /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ   (4*1024)        /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS   4          /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1           0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE      0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2           0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE      0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3           0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE      0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4           0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE      0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1           0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2           0x04000000 /* Flash Bank #2 */
+#define PHYS_FLASH_SIZE                0x02000000 /* 32 MB */
+#define PHYS_FLASH_BANK_SIZE   0x02000000 /* 32 MB Banks */
+#define PHYS_FLASH_SECT_SIZE   0x00040000 /* 256 KB sectors (x2) */
+
+#define CFG_DRAM_BASE          0xa0000000
+#define CFG_DRAM_SIZE          0x04000000
+
+#define CFG_FLASH_BASE         PHYS_FLASH_1
+
+#define FPGA_REGS_BASE_PHYSICAL 0x08000000
+
+/*
+ * GPIO settings
+ */
+#define CFG_GPSR0_VAL          0x00008000
+#define CFG_GPSR1_VAL          0x00FC0382
+#define CFG_GPSR2_VAL          0x0001FFFF
+#define CFG_GPCR0_VAL          0x00000000
+#define CFG_GPCR1_VAL          0x00000000
+#define CFG_GPCR2_VAL          0x00000000
+#define CFG_GPDR0_VAL          0x0060A800
+#define CFG_GPDR1_VAL          0x00FF0382
+#define CFG_GPDR2_VAL          0x0001C000
+#define CFG_GAFR0_L_VAL                0x98400000
+#define CFG_GAFR0_U_VAL                0x00002950
+#define CFG_GAFR1_L_VAL                0x000A9558
+#define CFG_GAFR1_U_VAL                0x0005AAAA
+#define CFG_GAFR2_L_VAL                0xA0000000
+#define CFG_GAFR2_U_VAL                0x00000002
+
+#define CFG_PSSR_VAL           0x20
+
+/*
+ * Memory settings
+ */
+#define CFG_MSC0_VAL           0x23F223F2
+#define CFG_MSC1_VAL           0x3FF1A441
+#define CFG_MSC2_VAL           0x7FF97FF1
+#define CFG_MDCNFG_VAL         0x00001AC9
+#define CFG_MDREFR_VAL         0x00018018
+#define CFG_MDMRS_VAL          0x00000000
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL           0x00000000
+#define CFG_MCMEM0_VAL         0x00010504
+#define CFG_MCMEM1_VAL         0x00010504
+#define CFG_MCATT0_VAL         0x00010504
+#define CFG_MCATT1_VAL         0x00010504
+#define CFG_MCIO0_VAL          0x00004715
+#define CFG_MCIO1_VAL          0x00004715
+
+#define _LED                   0x08000010
+#define LED_BLANK              0x08000040
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS    2       /* max number of memory banks           */
+#define CFG_MAX_FLASH_SECT     128  /* max number of sectors on one chip    */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT   (25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT   (25*CFG_HZ) /* Timeout for Flash Write */
+
+/* NOTE: many default partitioning schemes assume the kernel starts at the
+ * second sector, not an environment.  You have been warned!
+ */
+#define        CFG_MONITOR_LEN         PHYS_FLASH_SECT_SIZE
+#define CFG_ENV_IS_IN_FLASH    1
+#define CFG_ENV_ADDR           (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
+#define CFG_ENV_SECT_SIZE      PHYS_FLASH_SECT_SIZE
+#define CFG_ENV_SIZE           (PHYS_FLASH_SECT_SIZE / 16)
+
+
+/*
+ * FPGA Offsets
+ */
+#define WHOAMI_OFFSET          0x00
+#define HEXLED_OFFSET          0x10
+#define BLANKLED_OFFSET                0x40
+#define DISCRETELED_OFFSET     0x40
+#define CNFG_SWITCHES_OFFSET   0x50
+#define USER_SWITCHES_OFFSET   0x60
+#define MISC_WR_OFFSET         0x80
+#define MISC_RD_OFFSET         0x90
+#define INT_MASK_OFFSET                0xC0
+#define INT_CLEAR_OFFSET       0xD0
+#define GP_OFFSET              0x100
+
+#endif /* __CONFIG_H */