#define VD1_HDR2_MATRIXI_EN_CTRL 0x383b
#define VD1_HDR2_MATRIXO_EN_CTRL 0x383c
+#define VD2_HDR2_CTRL 0x3850
+#define VD2_HDR2_CLK_GATE 0x3851
+#define VD2_HDR2_MATRIXI_COEF00_01 0x3852
+#define VD2_HDR2_MATRIXI_COEF02_10 0x3853
+#define VD2_HDR2_MATRIXI_COEF11_12 0x3854
+#define VD2_HDR2_MATRIXI_COEF20_21 0x3855
+#define VD2_HDR2_MATRIXI_COEF22 0x3856
+#define VD2_HDR2_MATRIXI_COEF30_31 0x3857
+#define VD2_HDR2_MATRIXI_COEF32_40 0x3858
+#define VD2_HDR2_MATRIXI_COEF41_42 0x3859
+#define VD2_HDR2_MATRIXI_OFFSET0_1 0x385a
+#define VD2_HDR2_MATRIXI_OFFSET2 0x385b
+#define VD2_HDR2_MATRIXI_PRE_OFFSET0_1 0x385c
+#define VD2_HDR2_MATRIXI_PRE_OFFSET2 0x385d
+#define VD2_HDR2_MATRIXO_COEF00_01 0x385e
+#define VD2_HDR2_MATRIXO_COEF02_10 0x385f
+#define VD2_HDR2_MATRIXO_COEF11_12 0x3860
+#define VD2_HDR2_MATRIXO_COEF20_21 0x3861
+#define VD2_HDR2_MATRIXO_COEF22 0x3862
+#define VD2_HDR2_MATRIXO_COEF30_31 0x3863
+#define VD2_HDR2_MATRIXO_COEF32_40 0x3864
+#define VD2_HDR2_MATRIXO_COEF41_42 0x3865
+#define VD2_HDR2_MATRIXO_OFFSET0_1 0x3866
+#define VD2_HDR2_MATRIXO_OFFSET2 0x3867
+#define VD2_HDR2_MATRIXO_PRE_OFFSET0_1 0x3868
+#define VD2_HDR2_MATRIXO_PRE_OFFSET2 0x3869
+#define VD2_HDR2_MATRIXI_CLIP 0x386a
+#define VD2_HDR2_MATRIXO_CLIP 0x386b
+#define VD2_HDR2_CGAIN_OFFT 0x386c
+#define VD2_EOTF_LUT_ADDR_PORT 0x386e
+#define VD2_EOTF_LUT_DATA_PORT 0x386f
+#define VD2_OETF_LUT_ADDR_PORT 0x3870
+#define VD2_OETF_LUT_DATA_PORT 0x3871
+#define VD2_CGAIN_LUT_ADDR_PORT 0x3872
+#define VD2_CGAIN_LUT_DATA_PORT 0x3873
+#define VD2_HDR2_CGAIN_COEF0 0x3874
+#define VD2_HDR2_CGAIN_COEF1 0x3875
+#define VD2_OGAIN_LUT_ADDR_PORT 0x3876
+#define VD2_OGAIN_LUT_DATA_PORT 0x3877
+#define VD2_HDR2_ADPS_CTRL 0x3878
+#define VD2_HDR2_ADPS_ALPHA0 0x3879
+#define VD2_HDR2_ADPS_ALPHA1 0x387a
+#define VD2_HDR2_ADPS_BETA0 0x387b
+#define VD2_HDR2_ADPS_BETA1 0x387c
+#define VD2_HDR2_ADPS_BETA2 0x387d
+#define VD2_HDR2_ADPS_COEF0 0x387e
+#define VD2_HDR2_ADPS_COEF1 0x387f
+#define VD2_HDR2_GMUT_CTRL 0x3880
+#define VD2_HDR2_GMUT_COEF0 0x3881
+#define VD2_HDR2_GMUT_COEF1 0x3882
+#define VD2_HDR2_GMUT_COEF2 0x3883
+#define VD2_HDR2_GMUT_COEF3 0x3884
+#define VD2_HDR2_GMUT_COEF4 0x3885
+#define VD2_HDR2_PIPE_CTRL1 0x3886
+#define VD2_HDR2_PIPE_CTRL2 0x3887
+#define VD2_HDR2_PIPE_CTRL3 0x3888
+#define VD2_HDR2_PROC_WIN1 0x3889
+#define VD2_HDR2_PROC_WIN2 0x388a
+#define VD2_HDR2_MATRIXI_EN_CTRL 0x388b
+#define VD2_HDR2_MATRIXO_EN_CTRL 0x388c
+
#define OSD1_HDR2_CTRL 0x38a0
#define OSD1_HDR2_CLK_GATE 0x38a1
#define OSD1_HDR2_MATRIXI_COEF00_01 0x38a2
#define OSD1_HDR2_PROC_WIN2 0x38da
#define OSD1_HDR2_MATRIXI_EN_CTRL 0x38db
#define OSD1_HDR2_MATRIXO_EN_CTRL 0x38dc
+
+#define DI_HDR2_CTRL 0x3770
+#define DI_HDR2_CLK_GATE 0x3771
+#define DI_HDR2_MATRIXI_COEF00_01 0x3772
+#define DI_HDR2_MATRIXI_COEF02_10 0x3773
+#define DI_HDR2_MATRIXI_COEF11_12 0x3774
+#define DI_HDR2_MATRIXI_COEF20_21 0x3775
+#define DI_HDR2_MATRIXI_COEF22 0x3776
+#define DI_HDR2_MATRIXI_COEF30_31 0x3777
+#define DI_HDR2_MATRIXI_COEF32_40 0x3778
+#define DI_HDR2_MATRIXI_COEF41_42 0x3779
+#define DI_HDR2_MATRIXI_OFFSET0_1 0x377a
+#define DI_HDR2_MATRIXI_OFFSET2 0x377b
+#define DI_HDR2_MATRIXI_PRE_OFFSET0_1 0x377c
+#define DI_HDR2_MATRIXI_PRE_OFFSET2 0x377d
+#define DI_HDR2_MATRIXO_COEF00_01 0x377e
+#define DI_HDR2_MATRIXO_COEF02_10 0x377f
+#define DI_HDR2_MATRIXO_COEF11_12 0x3780
+#define DI_HDR2_MATRIXO_COEF20_21 0x3781
+#define DI_HDR2_MATRIXO_COEF22 0x3782
+#define DI_HDR2_MATRIXO_COEF30_31 0x3783
+#define DI_HDR2_MATRIXO_COEF32_40 0x3784
+#define DI_HDR2_MATRIXO_COEF41_42 0x3785
+#define DI_HDR2_MATRIXO_OFFSET0_1 0x3786
+#define DI_HDR2_MATRIXO_OFFSET2 0x3787
+#define DI_HDR2_MATRIXO_PRE_OFFSET0_1 0x3788
+#define DI_HDR2_MATRIXO_PRE_OFFSET2 0x3789
+#define DI_HDR2_MATRIXI_CLIP 0x378a
+#define DI_HDR2_MATRIXO_CLIP 0x378b
+#define DI_HDR2_CGAIN_OFFT 0x378c
+#define DI_EOTF_LUT_ADDR_PORT 0x378e
+#define DI_EOTF_LUT_DATA_PORT 0x378f
+#define DI_OETF_LUT_ADDR_PORT 0x3790
+#define DI_OETF_LUT_DATA_PORT 0x3791
+#define DI_CGAIN_LUT_ADDR_PORT 0x3792
+#define DI_CGAIN_LUT_DATA_PORT 0x3793
+#define DI_HDR2_CGAIN_COEF0 0x3794
+#define DI_HDR2_CGAIN_COEF1 0x3795
+#define DI_OGAIN_LUT_ADDR_PORT 0x3796
+#define DI_OGAIN_LUT_DATA_PORT 0x3797
+#define DI_HDR2_ADPS_CTRL 0x3798
+#define DI_HDR2_ADPS_ALPHA0 0x3799
+#define DI_HDR2_ADPS_ALPHA1 0x379a
+#define DI_HDR2_ADPS_BETA0 0x379b
+#define DI_HDR2_ADPS_BETA1 0x379c
+#define DI_HDR2_ADPS_BETA2 0x379d
+#define DI_HDR2_ADPS_COEF0 0x379e
+#define DI_HDR2_ADPS_COEF1 0x379f
+#define DI_HDR2_GMUT_CTRL 0x37a0
+#define DI_HDR2_GMUT_COEF0 0x37a1
+#define DI_HDR2_GMUT_COEF1 0x37a2
+#define DI_HDR2_GMUT_COEF2 0x37a3
+#define DI_HDR2_GMUT_COEF3 0x37a4
+#define DI_HDR2_GMUT_COEF4 0x37a5
+#define DI_HDR2_PIPE_CTRL1 0x37a6
+#define DI_HDR2_PIPE_CTRL2 0x37a7
+#define DI_HDR2_PIPE_CTRL3 0x37a8
+#define DI_HDR2_PROC_WIN1 0x37a9
+#define DI_HDR2_PROC_WIN2 0x37aa
+#define DI_HDR2_MATRIXI_EN_CTRL 0x37ab
+#define DI_HDR2_MATRIXO_EN_CTRL 0x37ac
+
+#define VDIN0_HDR2_CTRL 0x1280
+#define VDIN0_HDR2_CLK_GATE 0x1281
+#define VDIN0_HDR2_MATRIXI_COEF00_01 0x1282
+#define VDIN0_HDR2_MATRIXI_COEF02_10 0x1283
+#define VDIN0_HDR2_MATRIXI_COEF11_12 0x1284
+#define VDIN0_HDR2_MATRIXI_COEF20_21 0x1285
+#define VDIN0_HDR2_MATRIXI_COEF22 0x1286
+#define VDIN0_HDR2_MATRIXI_COEF30_31 0x1287
+#define VDIN0_HDR2_MATRIXI_COEF32_40 0x1288
+#define VDIN0_HDR2_MATRIXI_COEF41_42 0x1289
+#define VDIN0_HDR2_MATRIXI_OFFSET0_1 0x128a
+#define VDIN0_HDR2_MATRIXI_OFFSET2 0x128b
+#define VDIN0_HDR2_MATRIXI_PRE_OFFSET0_1 0x128c
+#define VDIN0_HDR2_MATRIXI_PRE_OFFSET2 0x128d
+#define VDIN0_HDR2_MATRIXO_COEF00_01 0x128e
+#define VDIN0_HDR2_MATRIXO_COEF02_10 0x128f
+#define VDIN0_HDR2_MATRIXO_COEF11_12 0x1290
+#define VDIN0_HDR2_MATRIXO_COEF20_21 0x1291
+#define VDIN0_HDR2_MATRIXO_COEF22 0x1292
+#define VDIN0_HDR2_MATRIXO_COEF30_31 0x1293
+#define VDIN0_HDR2_MATRIXO_COEF32_40 0x1294
+#define VDIN0_HDR2_MATRIXO_COEF41_42 0x1295
+#define VDIN0_HDR2_MATRIXO_OFFSET0_1 0x1296
+#define VDIN0_HDR2_MATRIXO_OFFSET2 0x1297
+#define VDIN0_HDR2_MATRIXO_PRE_OFFSET0_1 0x1298
+#define VDIN0_HDR2_MATRIXO_PRE_OFFSET2 0x1299
+#define VDIN0_HDR2_MATRIXI_CLIP 0x129a
+#define VDIN0_HDR2_MATRIXO_CLIP 0x129b
+#define VDIN0_HDR2_CGAIN_OFFT 0x129c
+#define VDIN0_EOTF_LUT_ADDR_PORT 0x129e
+#define VDIN0_EOTF_LUT_DATA_PORT 0x129f
+#define VDIN0_OETF_LUT_ADDR_PORT 0x12a0
+#define VDIN0_OETF_LUT_DATA_PORT 0x12a1
+#define VDIN0_CGAIN_LUT_ADDR_PORT 0x12a2
+#define VDIN0_CGAIN_LUT_DATA_PORT 0x12a3
+#define VDIN0_HDR2_CGAIN_COEF0 0x12a4
+#define VDIN0_HDR2_CGAIN_COEF1 0x12a5
+#define VDIN0_OGAIN_LUT_ADDR_PORT 0x12a6
+#define VDIN0_OGAIN_LUT_DATA_PORT 0x12a7
+#define VDIN0_HDR2_ADPS_CTRL 0x12a8
+#define VDIN0_HDR2_ADPS_ALPHA0 0x12a9
+#define VDIN0_HDR2_ADPS_ALPHA1 0x12aa
+#define VDIN0_HDR2_ADPS_BETA0 0x12ab
+#define VDIN0_HDR2_ADPS_BETA1 0x12ac
+#define VDIN0_HDR2_ADPS_BETA2 0x12ad
+#define VDIN0_HDR2_ADPS_COEF0 0x12ae
+#define VDIN0_HDR2_ADPS_COEF1 0x12af
+#define VDIN0_HDR2_GMUT_CTRL 0x12b0
+#define VDIN0_HDR2_GMUT_COEF0 0x12b1
+#define VDIN0_HDR2_GMUT_COEF1 0x12b2
+#define VDIN0_HDR2_GMUT_COEF2 0x12b3
+#define VDIN0_HDR2_GMUT_COEF3 0x12b4
+#define VDIN0_HDR2_GMUT_COEF4 0x12b5
+#define VDIN0_HDR2_PIPE_CTRL1 0x12b6
+#define VDIN0_HDR2_PIPE_CTRL2 0x12b7
+#define VDIN0_HDR2_PIPE_CTRL3 0x12b8
+#define VDIN0_HDR2_PROC_WIN1 0x12b9
+#define VDIN0_HDR2_PROC_WIN2 0x12ba
+#define VDIN0_HDR2_MATRIXI_EN_CTRL 0x12bb
+#define VDIN0_HDR2_MATRIXO_EN_CTRL 0x12bc
+
+#define VDIN1_HDR2_CTRL 0x1380
+#define VDIN1_HDR2_CLK_GATE 0x1381
+#define VDIN1_HDR2_MATRIXI_COEF00_01 0x1382
+#define VDIN1_HDR2_MATRIXI_COEF02_10 0x1383
+#define VDIN1_HDR2_MATRIXI_COEF11_12 0x1384
+#define VDIN1_HDR2_MATRIXI_COEF20_21 0x1385
+#define VDIN1_HDR2_MATRIXI_COEF22 0x1386
+#define VDIN1_HDR2_MATRIXI_COEF30_31 0x1387
+#define VDIN1_HDR2_MATRIXI_COEF32_40 0x1388
+#define VDIN1_HDR2_MATRIXI_COEF41_42 0x1389
+#define VDIN1_HDR2_MATRIXI_OFFSET0_1 0x138a
+#define VDIN1_HDR2_MATRIXI_OFFSET2 0x138b
+#define VDIN1_HDR2_MATRIXI_PRE_OFFSET0_1 0x138c
+#define VDIN1_HDR2_MATRIXI_PRE_OFFSET2 0x138d
+#define VDIN1_HDR2_MATRIXO_COEF00_01 0x138e
+#define VDIN1_HDR2_MATRIXO_COEF02_10 0x138f
+#define VDIN1_HDR2_MATRIXO_COEF11_12 0x1390
+#define VDIN1_HDR2_MATRIXO_COEF20_21 0x1391
+#define VDIN1_HDR2_MATRIXO_COEF22 0x1392
+#define VDIN1_HDR2_MATRIXO_COEF30_31 0x1393
+#define VDIN1_HDR2_MATRIXO_COEF32_40 0x1394
+#define VDIN1_HDR2_MATRIXO_COEF41_42 0x1395
+#define VDIN1_HDR2_MATRIXO_OFFSET0_1 0x1396
+#define VDIN1_HDR2_MATRIXO_OFFSET2 0x1397
+#define VDIN1_HDR2_MATRIXO_PRE_OFFSET0_1 0x1398
+#define VDIN1_HDR2_MATRIXO_PRE_OFFSET2 0x1399
+#define VDIN1_HDR2_MATRIXI_CLIP 0x139a
+#define VDIN1_HDR2_MATRIXO_CLIP 0x139b
+#define VDIN1_HDR2_CGAIN_OFFT 0x139c
+#define VDIN1_EOTF_LUT_ADDR_PORT 0x139e
+#define VDIN1_EOTF_LUT_DATA_PORT 0x139f
+#define VDIN1_OETF_LUT_ADDR_PORT 0x13a0
+#define VDIN1_OETF_LUT_DATA_PORT 0x13a1
+#define VDIN1_CGAIN_LUT_ADDR_PORT 0x13a2
+#define VDIN1_CGAIN_LUT_DATA_PORT 0x13a3
+#define VDIN1_HDR2_CGAIN_COEF0 0x13a4
+#define VDIN1_HDR2_CGAIN_COEF1 0x13a5
+#define VDIN1_OGAIN_LUT_ADDR_PORT 0x13a6
+#define VDIN1_OGAIN_LUT_DATA_PORT 0x13a7
+#define VDIN1_HDR2_ADPS_CTRL 0x13a8
+#define VDIN1_HDR2_ADPS_ALPHA0 0x13a9
+#define VDIN1_HDR2_ADPS_ALPHA1 0x13aa
+#define VDIN1_HDR2_ADPS_BETA0 0x13ab
+#define VDIN1_HDR2_ADPS_BETA1 0x13ac
+#define VDIN1_HDR2_ADPS_BETA2 0x13ad
+#define VDIN1_HDR2_ADPS_COEF0 0x13ae
+#define VDIN1_HDR2_ADPS_COEF1 0x13af
+#define VDIN1_HDR2_GMUT_CTRL 0x13b0
+#define VDIN1_HDR2_GMUT_COEF0 0x13b1
+#define VDIN1_HDR2_GMUT_COEF1 0x13b2
+#define VDIN1_HDR2_GMUT_COEF2 0x13b3
+#define VDIN1_HDR2_GMUT_COEF3 0x13b4
+#define VDIN1_HDR2_GMUT_COEF4 0x13b5
+#define VDIN1_HDR2_PIPE_CTRL1 0x13b6
+#define VDIN1_HDR2_PIPE_CTRL2 0x13b7
+#define VDIN1_HDR2_PIPE_CTRL3 0x13b8
+#define VDIN1_HDR2_PROC_WIN1 0x13b9
+#define VDIN1_HDR2_PROC_WIN2 0x13ba
+#define VDIN1_HDR2_MATRIXI_EN_CTRL 0x13bb
+#define VDIN1_HDR2_MATRIXO_EN_CTRL 0x13bc
#endif
GMUT_COEF4 = VD1_HDR2_GMUT_COEF4;
hdr_ctrl = VD1_HDR2_CTRL;
+ } else if (module_sel & VD2_HDR) {
+ MATRIXI_COEF00_01 = VDIN1_HDR2_MATRIXI_COEF00_01;
+ MATRIXI_COEF00_01 = VDIN1_HDR2_MATRIXI_COEF00_01;
+ MATRIXI_COEF02_10 = VDIN1_HDR2_MATRIXI_COEF02_10;
+ MATRIXI_COEF11_12 = VDIN1_HDR2_MATRIXI_COEF11_12;
+ MATRIXI_COEF20_21 = VDIN1_HDR2_MATRIXI_COEF20_21;
+ MATRIXI_COEF22 = VDIN1_HDR2_MATRIXI_COEF22;
+ MATRIXI_COEF30_31 = VDIN1_HDR2_MATRIXI_COEF30_31;
+ MATRIXI_COEF32_40 = VDIN1_HDR2_MATRIXI_COEF32_40;
+ MATRIXI_COEF41_42 = VDIN1_HDR2_MATRIXI_COEF41_42;
+ MATRIXI_OFFSET0_1 = VDIN1_HDR2_MATRIXI_OFFSET0_1;
+ MATRIXI_OFFSET2 = VDIN1_HDR2_MATRIXI_OFFSET2;
+ MATRIXI_PRE_OFFSET0_1 = VDIN1_HDR2_MATRIXI_PRE_OFFSET0_1;
+ MATRIXI_PRE_OFFSET2 = VDIN1_HDR2_MATRIXI_PRE_OFFSET2;
+ MATRIXI_CLIP = VDIN1_HDR2_MATRIXI_CLIP;
+ MATRIXI_EN_CTRL = VDIN1_HDR2_MATRIXI_EN_CTRL;
+
+ MATRIXO_COEF00_01 = VDIN1_HDR2_MATRIXO_COEF00_01;
+ MATRIXO_COEF00_01 = VDIN1_HDR2_MATRIXO_COEF00_01;
+ MATRIXO_COEF02_10 = VDIN1_HDR2_MATRIXO_COEF02_10;
+ MATRIXO_COEF11_12 = VDIN1_HDR2_MATRIXO_COEF11_12;
+ MATRIXO_COEF20_21 = VDIN1_HDR2_MATRIXO_COEF20_21;
+ MATRIXO_COEF22 = VDIN1_HDR2_MATRIXO_COEF22;
+ MATRIXO_COEF30_31 = VDIN1_HDR2_MATRIXO_COEF30_31;
+ MATRIXO_COEF32_40 = VDIN1_HDR2_MATRIXO_COEF32_40;
+ MATRIXO_COEF41_42 = VDIN1_HDR2_MATRIXO_COEF41_42;
+ MATRIXO_OFFSET0_1 = VDIN1_HDR2_MATRIXO_OFFSET0_1;
+ MATRIXO_OFFSET2 = VDIN1_HDR2_MATRIXO_OFFSET2;
+ MATRIXO_PRE_OFFSET0_1 = VDIN1_HDR2_MATRIXO_PRE_OFFSET0_1;
+ MATRIXO_PRE_OFFSET2 = VDIN1_HDR2_MATRIXO_PRE_OFFSET2;
+ MATRIXO_CLIP = VDIN1_HDR2_MATRIXO_CLIP;
+ MATRIXO_EN_CTRL = VDIN1_HDR2_MATRIXO_EN_CTRL;
+
+ CGAIN_OFFT = VDIN1_HDR2_CGAIN_OFFT;
+ CGAIN_COEF0 = VDIN1_HDR2_CGAIN_COEF0;
+ CGAIN_COEF1 = VDIN1_HDR2_CGAIN_COEF1;
+ ADPS_CTRL = VDIN1_HDR2_ADPS_CTRL;
+ ADPS_ALPHA0 = VDIN1_HDR2_ADPS_ALPHA0;
+ ADPS_ALPHA1 = VDIN1_HDR2_ADPS_ALPHA1;
+ ADPS_BETA0 = VDIN1_HDR2_ADPS_BETA0;
+ ADPS_BETA1 = VDIN1_HDR2_ADPS_BETA1;
+ ADPS_BETA2 = VDIN1_HDR2_ADPS_BETA2;
+ ADPS_COEF0 = VDIN1_HDR2_ADPS_COEF0;
+ ADPS_COEF1 = VDIN1_HDR2_ADPS_COEF1;
+ GMUT_CTRL = VDIN1_HDR2_GMUT_CTRL;
+ GMUT_COEF0 = VDIN1_HDR2_GMUT_COEF0;
+ GMUT_COEF1 = VDIN1_HDR2_GMUT_COEF1;
+ GMUT_COEF2 = VDIN1_HDR2_GMUT_COEF2;
+ GMUT_COEF3 = VDIN1_HDR2_GMUT_COEF3;
+ GMUT_COEF4 = VDIN1_HDR2_GMUT_COEF4;
+
+ hdr_ctrl = VDIN1_HDR2_CTRL;
} else if (module_sel & OSD1_HDR) {
MATRIXI_COEF00_01 = OSD1_HDR2_MATRIXI_COEF00_01;
MATRIXI_COEF00_01 = OSD1_HDR2_MATRIXI_COEF00_01;
GMUT_COEF4 = OSD1_HDR2_GMUT_COEF4;
hdr_ctrl = OSD1_HDR2_CTRL;
+ } else if (module_sel & DI_HDR) {
+ MATRIXI_COEF00_01 = DI_HDR2_MATRIXI_COEF00_01;
+ MATRIXI_COEF00_01 = DI_HDR2_MATRIXI_COEF00_01;
+ MATRIXI_COEF02_10 = DI_HDR2_MATRIXI_COEF02_10;
+ MATRIXI_COEF11_12 = DI_HDR2_MATRIXI_COEF11_12;
+ MATRIXI_COEF20_21 = DI_HDR2_MATRIXI_COEF20_21;
+ MATRIXI_COEF22 = DI_HDR2_MATRIXI_COEF22;
+ MATRIXI_COEF30_31 = DI_HDR2_MATRIXI_COEF30_31;
+ MATRIXI_COEF32_40 = DI_HDR2_MATRIXI_COEF32_40;
+ MATRIXI_COEF41_42 = DI_HDR2_MATRIXI_COEF41_42;
+ MATRIXI_OFFSET0_1 = DI_HDR2_MATRIXI_OFFSET0_1;
+ MATRIXI_OFFSET2 = DI_HDR2_MATRIXI_OFFSET2;
+ MATRIXI_PRE_OFFSET0_1 = DI_HDR2_MATRIXI_PRE_OFFSET0_1;
+ MATRIXI_PRE_OFFSET2 = DI_HDR2_MATRIXI_PRE_OFFSET2;
+ MATRIXI_CLIP = DI_HDR2_MATRIXI_CLIP;
+ MATRIXI_EN_CTRL = DI_HDR2_MATRIXI_EN_CTRL;
+
+ MATRIXO_COEF00_01 = DI_HDR2_MATRIXO_COEF00_01;
+ MATRIXO_COEF00_01 = DI_HDR2_MATRIXO_COEF00_01;
+ MATRIXO_COEF02_10 = DI_HDR2_MATRIXO_COEF02_10;
+ MATRIXO_COEF11_12 = DI_HDR2_MATRIXO_COEF11_12;
+ MATRIXO_COEF20_21 = DI_HDR2_MATRIXO_COEF20_21;
+ MATRIXO_COEF22 = DI_HDR2_MATRIXO_COEF22;
+ MATRIXO_COEF30_31 = DI_HDR2_MATRIXO_COEF30_31;
+ MATRIXO_COEF32_40 = DI_HDR2_MATRIXO_COEF32_40;
+ MATRIXO_COEF41_42 = DI_HDR2_MATRIXO_COEF41_42;
+ MATRIXO_OFFSET0_1 = DI_HDR2_MATRIXO_OFFSET0_1;
+ MATRIXO_OFFSET2 = DI_HDR2_MATRIXO_OFFSET2;
+ MATRIXO_PRE_OFFSET0_1 = DI_HDR2_MATRIXO_PRE_OFFSET0_1;
+ MATRIXO_PRE_OFFSET2 = DI_HDR2_MATRIXO_PRE_OFFSET2;
+ MATRIXO_CLIP = DI_HDR2_MATRIXO_CLIP;
+ MATRIXO_EN_CTRL = DI_HDR2_MATRIXO_EN_CTRL;
+
+ CGAIN_OFFT = DI_HDR2_CGAIN_OFFT;
+ CGAIN_COEF0 = DI_HDR2_CGAIN_COEF0;
+ CGAIN_COEF1 = DI_HDR2_CGAIN_COEF1;
+ ADPS_CTRL = DI_HDR2_ADPS_CTRL;
+ ADPS_ALPHA0 = DI_HDR2_ADPS_ALPHA0;
+ ADPS_ALPHA1 = DI_HDR2_ADPS_ALPHA1;
+ ADPS_BETA0 = DI_HDR2_ADPS_BETA0;
+ ADPS_BETA1 = DI_HDR2_ADPS_BETA1;
+ ADPS_BETA2 = DI_HDR2_ADPS_BETA2;
+ ADPS_COEF0 = DI_HDR2_ADPS_COEF0;
+ ADPS_COEF1 = DI_HDR2_ADPS_COEF1;
+ GMUT_CTRL = DI_HDR2_GMUT_CTRL;
+ GMUT_COEF0 = DI_HDR2_GMUT_COEF0;
+ GMUT_COEF1 = DI_HDR2_GMUT_COEF1;
+ GMUT_COEF2 = DI_HDR2_GMUT_COEF2;
+ GMUT_COEF3 = DI_HDR2_GMUT_COEF3;
+ GMUT_COEF4 = DI_HDR2_GMUT_COEF4;
+
+ hdr_ctrl = DI_HDR2_CTRL;
+ } else if (module_sel & VDIN0_HDR) {
+ MATRIXI_COEF00_01 = VDIN0_HDR2_MATRIXI_COEF00_01;
+ MATRIXI_COEF00_01 = VDIN0_HDR2_MATRIXI_COEF00_01;
+ MATRIXI_COEF02_10 = VDIN0_HDR2_MATRIXI_COEF02_10;
+ MATRIXI_COEF11_12 = VDIN0_HDR2_MATRIXI_COEF11_12;
+ MATRIXI_COEF20_21 = VDIN0_HDR2_MATRIXI_COEF20_21;
+ MATRIXI_COEF22 = VDIN0_HDR2_MATRIXI_COEF22;
+ MATRIXI_COEF30_31 = VDIN0_HDR2_MATRIXI_COEF30_31;
+ MATRIXI_COEF32_40 = VDIN0_HDR2_MATRIXI_COEF32_40;
+ MATRIXI_COEF41_42 = VDIN0_HDR2_MATRIXI_COEF41_42;
+ MATRIXI_OFFSET0_1 = VDIN0_HDR2_MATRIXI_OFFSET0_1;
+ MATRIXI_OFFSET2 = VDIN0_HDR2_MATRIXI_OFFSET2;
+ MATRIXI_PRE_OFFSET0_1 = VDIN0_HDR2_MATRIXI_PRE_OFFSET0_1;
+ MATRIXI_PRE_OFFSET2 = VDIN0_HDR2_MATRIXI_PRE_OFFSET2;
+ MATRIXI_CLIP = VDIN0_HDR2_MATRIXI_CLIP;
+ MATRIXI_EN_CTRL = VDIN0_HDR2_MATRIXI_EN_CTRL;
+
+ MATRIXO_COEF00_01 = VDIN0_HDR2_MATRIXO_COEF00_01;
+ MATRIXO_COEF00_01 = VDIN0_HDR2_MATRIXO_COEF00_01;
+ MATRIXO_COEF02_10 = VDIN0_HDR2_MATRIXO_COEF02_10;
+ MATRIXO_COEF11_12 = VDIN0_HDR2_MATRIXO_COEF11_12;
+ MATRIXO_COEF20_21 = VDIN0_HDR2_MATRIXO_COEF20_21;
+ MATRIXO_COEF22 = VDIN0_HDR2_MATRIXO_COEF22;
+ MATRIXO_COEF30_31 = VDIN0_HDR2_MATRIXO_COEF30_31;
+ MATRIXO_COEF32_40 = VDIN0_HDR2_MATRIXO_COEF32_40;
+ MATRIXO_COEF41_42 = VDIN0_HDR2_MATRIXO_COEF41_42;
+ MATRIXO_OFFSET0_1 = VDIN0_HDR2_MATRIXO_OFFSET0_1;
+ MATRIXO_OFFSET2 = VDIN0_HDR2_MATRIXO_OFFSET2;
+ MATRIXO_PRE_OFFSET0_1 = VDIN0_HDR2_MATRIXO_PRE_OFFSET0_1;
+ MATRIXO_PRE_OFFSET2 = VDIN0_HDR2_MATRIXO_PRE_OFFSET2;
+ MATRIXO_CLIP = VDIN0_HDR2_MATRIXO_CLIP;
+ MATRIXO_EN_CTRL = VDIN0_HDR2_MATRIXO_EN_CTRL;
+
+ CGAIN_OFFT = VDIN0_HDR2_CGAIN_OFFT;
+ CGAIN_COEF0 = VDIN0_HDR2_CGAIN_COEF0;
+ CGAIN_COEF1 = VDIN0_HDR2_CGAIN_COEF1;
+ ADPS_CTRL = VDIN0_HDR2_ADPS_CTRL;
+ ADPS_ALPHA0 = VDIN0_HDR2_ADPS_ALPHA0;
+ ADPS_ALPHA1 = VDIN0_HDR2_ADPS_ALPHA1;
+ ADPS_BETA0 = VDIN0_HDR2_ADPS_BETA0;
+ ADPS_BETA1 = VDIN0_HDR2_ADPS_BETA1;
+ ADPS_BETA2 = VDIN0_HDR2_ADPS_BETA2;
+ ADPS_COEF0 = VDIN0_HDR2_ADPS_COEF0;
+ ADPS_COEF1 = VDIN0_HDR2_ADPS_COEF1;
+ GMUT_CTRL = VDIN0_HDR2_GMUT_CTRL;
+ GMUT_COEF0 = VDIN0_HDR2_GMUT_COEF0;
+ GMUT_COEF1 = VDIN0_HDR2_GMUT_COEF1;
+ GMUT_COEF2 = VDIN0_HDR2_GMUT_COEF2;
+ GMUT_COEF3 = VDIN0_HDR2_GMUT_COEF3;
+ GMUT_COEF4 = VDIN0_HDR2_GMUT_COEF4;
+
+ hdr_ctrl = VDIN0_HDR2_CTRL;
+ } else if (module_sel & VDIN1_HDR) {
+ MATRIXI_COEF00_01 = VDIN1_HDR2_MATRIXI_COEF00_01;
+ MATRIXI_COEF00_01 = VDIN1_HDR2_MATRIXI_COEF00_01;
+ MATRIXI_COEF02_10 = VDIN1_HDR2_MATRIXI_COEF02_10;
+ MATRIXI_COEF11_12 = VDIN1_HDR2_MATRIXI_COEF11_12;
+ MATRIXI_COEF20_21 = VDIN1_HDR2_MATRIXI_COEF20_21;
+ MATRIXI_COEF22 = VDIN1_HDR2_MATRIXI_COEF22;
+ MATRIXI_COEF30_31 = VDIN1_HDR2_MATRIXI_COEF30_31;
+ MATRIXI_COEF32_40 = VDIN1_HDR2_MATRIXI_COEF32_40;
+ MATRIXI_COEF41_42 = VDIN1_HDR2_MATRIXI_COEF41_42;
+ MATRIXI_OFFSET0_1 = VDIN1_HDR2_MATRIXI_OFFSET0_1;
+ MATRIXI_OFFSET2 = VDIN1_HDR2_MATRIXI_OFFSET2;
+ MATRIXI_PRE_OFFSET0_1 = VDIN1_HDR2_MATRIXI_PRE_OFFSET0_1;
+ MATRIXI_PRE_OFFSET2 = VDIN1_HDR2_MATRIXI_PRE_OFFSET2;
+ MATRIXI_CLIP = VDIN1_HDR2_MATRIXI_CLIP;
+ MATRIXI_EN_CTRL = VDIN1_HDR2_MATRIXI_EN_CTRL;
+
+ MATRIXO_COEF00_01 = VDIN1_HDR2_MATRIXO_COEF00_01;
+ MATRIXO_COEF00_01 = VDIN1_HDR2_MATRIXO_COEF00_01;
+ MATRIXO_COEF02_10 = VDIN1_HDR2_MATRIXO_COEF02_10;
+ MATRIXO_COEF11_12 = VDIN1_HDR2_MATRIXO_COEF11_12;
+ MATRIXO_COEF20_21 = VDIN1_HDR2_MATRIXO_COEF20_21;
+ MATRIXO_COEF22 = VDIN1_HDR2_MATRIXO_COEF22;
+ MATRIXO_COEF30_31 = VDIN1_HDR2_MATRIXO_COEF30_31;
+ MATRIXO_COEF32_40 = VDIN1_HDR2_MATRIXO_COEF32_40;
+ MATRIXO_COEF41_42 = VDIN1_HDR2_MATRIXO_COEF41_42;
+ MATRIXO_OFFSET0_1 = VDIN1_HDR2_MATRIXO_OFFSET0_1;
+ MATRIXO_OFFSET2 = VDIN1_HDR2_MATRIXO_OFFSET2;
+ MATRIXO_PRE_OFFSET0_1 = VDIN1_HDR2_MATRIXO_PRE_OFFSET0_1;
+ MATRIXO_PRE_OFFSET2 = VDIN1_HDR2_MATRIXO_PRE_OFFSET2;
+ MATRIXO_CLIP = VDIN1_HDR2_MATRIXO_CLIP;
+ MATRIXO_EN_CTRL = VDIN1_HDR2_MATRIXO_EN_CTRL;
+
+ CGAIN_OFFT = VDIN1_HDR2_CGAIN_OFFT;
+ CGAIN_COEF0 = VDIN1_HDR2_CGAIN_COEF0;
+ CGAIN_COEF1 = VDIN1_HDR2_CGAIN_COEF1;
+ ADPS_CTRL = VDIN1_HDR2_ADPS_CTRL;
+ ADPS_ALPHA0 = VDIN1_HDR2_ADPS_ALPHA0;
+ ADPS_ALPHA1 = VDIN1_HDR2_ADPS_ALPHA1;
+ ADPS_BETA0 = VDIN1_HDR2_ADPS_BETA0;
+ ADPS_BETA1 = VDIN1_HDR2_ADPS_BETA1;
+ ADPS_BETA2 = VDIN1_HDR2_ADPS_BETA2;
+ ADPS_COEF0 = VDIN1_HDR2_ADPS_COEF0;
+ ADPS_COEF1 = VDIN1_HDR2_ADPS_COEF1;
+ GMUT_CTRL = VDIN1_HDR2_GMUT_CTRL;
+ GMUT_COEF0 = VDIN1_HDR2_GMUT_COEF0;
+ GMUT_COEF1 = VDIN1_HDR2_GMUT_COEF1;
+ GMUT_COEF2 = VDIN1_HDR2_GMUT_COEF2;
+ GMUT_COEF3 = VDIN1_HDR2_GMUT_COEF3;
+ GMUT_COEF4 = VDIN1_HDR2_GMUT_COEF4;
+
+ hdr_ctrl = VDIN1_HDR2_CTRL;
}
WRITE_VPP_REG_BITS(hdr_ctrl, hdr_mtx_param->mtx_on, 13, 1);
eotf_lut_addr_port = VD1_EOTF_LUT_ADDR_PORT;
eotf_lut_data_port = VD1_EOTF_LUT_DATA_PORT;
hdr_ctrl = VD1_HDR2_CTRL;
+ } else if (module_sel & VD2_HDR) {
+ eotf_lut_addr_port = VD2_EOTF_LUT_ADDR_PORT;
+ eotf_lut_data_port = VD2_EOTF_LUT_DATA_PORT;
+ hdr_ctrl = VD2_HDR2_CTRL;
} else if (module_sel & OSD1_HDR) {
eotf_lut_addr_port = OSD1_EOTF_LUT_ADDR_PORT;
eotf_lut_data_port = OSD1_EOTF_LUT_DATA_PORT;
hdr_ctrl = OSD1_HDR2_CTRL;
+ } else if (module_sel & DI_HDR) {
+ eotf_lut_addr_port = DI_EOTF_LUT_ADDR_PORT;
+ eotf_lut_data_port = DI_EOTF_LUT_DATA_PORT;
+ hdr_ctrl = DI_HDR2_CTRL;
+ } else if (module_sel & VDIN0_HDR) {
+ eotf_lut_addr_port = VDIN0_EOTF_LUT_ADDR_PORT;
+ eotf_lut_data_port = VDIN0_EOTF_LUT_DATA_PORT;
+ hdr_ctrl = VDIN0_HDR2_CTRL;
+ } else if (module_sel & VDIN1_HDR) {
+ eotf_lut_addr_port = VDIN1_EOTF_LUT_ADDR_PORT;
+ eotf_lut_data_port = VDIN1_EOTF_LUT_DATA_PORT;
+ hdr_ctrl = VDIN1_HDR2_CTRL;
}
for (i = 0; i < HDR2_EOTF_LUT_SIZE; i++)
ootf_lut_addr_port = VD1_OGAIN_LUT_ADDR_PORT;
ootf_lut_data_port = VD1_OGAIN_LUT_DATA_PORT;
hdr_ctrl = VD1_HDR2_CTRL;
+ } else if (module_sel & VD2_HDR) {
+ ootf_lut_addr_port = VD2_OGAIN_LUT_ADDR_PORT;
+ ootf_lut_data_port = VD2_OGAIN_LUT_DATA_PORT;
+ hdr_ctrl = VD2_HDR2_CTRL;
} else if (module_sel & OSD1_HDR) {
ootf_lut_addr_port = OSD1_OGAIN_LUT_ADDR_PORT;
ootf_lut_data_port = OSD1_OGAIN_LUT_DATA_PORT;
hdr_ctrl = OSD1_HDR2_CTRL;
+ } else if (module_sel & DI_HDR) {
+ ootf_lut_addr_port = DI_OGAIN_LUT_ADDR_PORT;
+ ootf_lut_data_port = DI_OGAIN_LUT_DATA_PORT;
+ hdr_ctrl = DI_HDR2_CTRL;
+ } else if (module_sel & VDIN0_HDR) {
+ ootf_lut_addr_port = VDIN0_OGAIN_LUT_ADDR_PORT;
+ ootf_lut_data_port = VDIN0_OGAIN_LUT_DATA_PORT;
+ hdr_ctrl = VDIN0_HDR2_CTRL;
+ } else if (module_sel & VDIN1_HDR) {
+ ootf_lut_addr_port = VDIN1_OGAIN_LUT_ADDR_PORT;
+ ootf_lut_data_port = VDIN1_OGAIN_LUT_DATA_PORT;
+ hdr_ctrl = VDIN1_HDR2_CTRL;
}
for (i = 0; i < HDR2_OOTF_LUT_SIZE; i++)
oetf_lut_addr_port = VD1_OETF_LUT_ADDR_PORT;
oetf_lut_data_port = VD1_OETF_LUT_DATA_PORT;
hdr_ctrl = VD1_HDR2_CTRL;
+ } else if (module_sel & VD2_HDR) {
+ oetf_lut_addr_port = VD2_OETF_LUT_ADDR_PORT;
+ oetf_lut_data_port = VD2_OETF_LUT_DATA_PORT;
+ hdr_ctrl = VD2_HDR2_CTRL;
} else if (module_sel & OSD1_HDR) {
oetf_lut_addr_port = OSD1_OETF_LUT_ADDR_PORT;
oetf_lut_data_port = OSD1_OETF_LUT_DATA_PORT;
hdr_ctrl = OSD1_HDR2_CTRL;
+ } else if (module_sel & DI_HDR) {
+ oetf_lut_addr_port = DI_OETF_LUT_ADDR_PORT;
+ oetf_lut_data_port = DI_OETF_LUT_DATA_PORT;
+ hdr_ctrl = DI_HDR2_CTRL;
+ } else if (module_sel & VDIN0_HDR) {
+ oetf_lut_addr_port = VDIN0_OETF_LUT_ADDR_PORT;
+ oetf_lut_data_port = VDIN0_OETF_LUT_DATA_PORT;
+ hdr_ctrl = VDIN0_HDR2_CTRL;
+ } else if (module_sel & VDIN1_HDR) {
+ oetf_lut_addr_port = VDIN1_OETF_LUT_ADDR_PORT;
+ oetf_lut_data_port = VDIN1_OETF_LUT_DATA_PORT;
+ hdr_ctrl = VDIN1_HDR2_CTRL;
}
for (i = 0; i < HDR2_OETF_LUT_SIZE; i++)
cgain_lut_addr_port = VD1_CGAIN_LUT_ADDR_PORT;
cgain_lut_data_port = VD1_CGAIN_LUT_DATA_PORT;
hdr_ctrl = VD1_HDR2_CTRL;
+ } else if (module_sel & VD2_HDR) {
+ cgain_lut_addr_port = VD2_CGAIN_LUT_ADDR_PORT;
+ cgain_lut_data_port = VD2_CGAIN_LUT_DATA_PORT;
+ hdr_ctrl = VD2_HDR2_CTRL;
} else if (module_sel & OSD1_HDR) {
cgain_lut_addr_port = OSD1_CGAIN_LUT_ADDR_PORT;
cgain_lut_data_port = OSD1_CGAIN_LUT_DATA_PORT;
hdr_ctrl = OSD1_HDR2_CTRL;
+ } else if (module_sel & DI_HDR) {
+ cgain_lut_addr_port = DI_CGAIN_LUT_ADDR_PORT;
+ cgain_lut_data_port = DI_CGAIN_LUT_DATA_PORT;
+ hdr_ctrl = DI_HDR2_CTRL;
+ } else if (module_sel & VDIN0_HDR) {
+ cgain_lut_addr_port = VDIN0_CGAIN_LUT_ADDR_PORT;
+ cgain_lut_data_port = VDIN0_CGAIN_LUT_DATA_PORT;
+ hdr_ctrl = VDIN0_HDR2_CTRL;
+ } else if (module_sel & VDIN1_HDR) {
+ cgain_lut_addr_port = VDIN1_CGAIN_LUT_ADDR_PORT;
+ cgain_lut_data_port = VDIN1_CGAIN_LUT_DATA_PORT;
+ hdr_ctrl = VDIN1_HDR2_CTRL;
}
-
for (i = 0; i < HDR2_CGAIN_LUT_SIZE; i++)
lut[i] = hdr_lut_param->cgain_lut[i];
projects / platform / kernel / linux-amlogic.git / commitdiff