intel/aux_map: correctly program tiling mode for Ys
authorLionel Landwerlin <lionel.g.landwerlin@intel.com>
Wed, 28 Jun 2023 06:32:54 +0000 (09:32 +0300)
committerMarge Bot <emma+marge@anholt.net>
Fri, 1 Sep 2023 23:22:18 +0000 (23:22 +0000)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>

src/intel/common/intel_aux_map.c

index ba04423..c76e693 100644 (file)
@@ -456,7 +456,8 @@ get_bpp_encoding(enum isl_format format)
    }
 }
 
-#define INTEL_AUX_MAP_ENTRY_Y_TILED_BIT  (0x1ull << 52)
+#define INTEL_AUX_MAP_ENTRY_Ys_TILED_BIT  (0x0ull << 52)
+#define INTEL_AUX_MAP_ENTRY_Y_TILED_BIT   (0x1ull << 52)
 
 uint64_t
 intel_aux_map_format_bits(enum isl_tiling tiling, enum isl_format format,
@@ -474,11 +475,19 @@ intel_aux_map_format_bits(enum isl_tiling tiling, enum isl_format format,
               isl_format_get_name(format),
               isl_format_get_aux_map_encoding(format));
 
+   assert(tiling == ISL_TILING_ICL_Ys ||
+          tiling == ISL_TILING_ICL_Yf ||
+          tiling == ISL_TILING_Y0);
+
    uint64_t format_bits =
       ((uint64_t)isl_format_get_aux_map_encoding(format) << 58) |
       ((uint64_t)(plane > 0) << 57) |
       ((uint64_t)get_bpp_encoding(format) << 54) |
-      INTEL_AUX_MAP_ENTRY_Y_TILED_BIT;
+      /* TODO: We assume that Yf is not Tiled-Ys, but waiting on
+       *       clarification
+       */
+      (tiling == ISL_TILING_ICL_Ys ? INTEL_AUX_MAP_ENTRY_Ys_TILED_BIT :
+                                     INTEL_AUX_MAP_ENTRY_Y_TILED_BIT);
 
    assert((format_bits & INTEL_AUX_MAP_FORMAT_BITS_MASK) == format_bits);