drm/vc4: hvs: Use switch statement to simplify enabling/disabling irq
authorMaxime Ripard <maxime@cerno.tech>
Fri, 17 Feb 2023 14:07:29 +0000 (15:07 +0100)
committerDom Cobley <popcornmix@gmail.com>
Mon, 19 Feb 2024 11:34:54 +0000 (11:34 +0000)
Since we'll support BCM2712 soon, let's move the logic to enable and
disable the end-of-frame interrupts to a switch to extend it more
easily.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
drivers/gpu/drm/vc4/vc4_hvs.c

index fd075c9..dd7a647 100644 (file)
@@ -416,24 +416,46 @@ static void vc4_hvs_irq_enable_eof(const struct vc4_hvs *hvs,
                                   unsigned int channel)
 {
        struct vc4_dev *vc4 = hvs->vc4;
-       u32 irq_mask = vc4->gen == VC4_GEN_5 ?
-               SCALER5_DISPCTRL_DSPEIEOF(channel) :
-               SCALER_DISPCTRL_DSPEIEOF(channel);
 
-       HVS_WRITE(SCALER_DISPCTRL,
-                 HVS_READ(SCALER_DISPCTRL) | irq_mask);
+       switch (vc4->gen) {
+       case VC4_GEN_4:
+               HVS_WRITE(SCALER_DISPCTRL,
+                         HVS_READ(SCALER_DISPCTRL) |
+                         SCALER_DISPCTRL_DSPEIEOF(channel));
+               break;
+
+       case VC4_GEN_5:
+               HVS_WRITE(SCALER_DISPCTRL,
+                         HVS_READ(SCALER_DISPCTRL) |
+                         SCALER5_DISPCTRL_DSPEIEOF(channel));
+               break;
+
+       default:
+               break;
+       }
 }
 
 static void vc4_hvs_irq_clear_eof(const struct vc4_hvs *hvs,
                                  unsigned int channel)
 {
        struct vc4_dev *vc4 = hvs->vc4;
-       u32 irq_mask = vc4->gen == VC4_GEN_5 ?
-               SCALER5_DISPCTRL_DSPEIEOF(channel) :
-               SCALER_DISPCTRL_DSPEIEOF(channel);
 
-       HVS_WRITE(SCALER_DISPCTRL,
-                 HVS_READ(SCALER_DISPCTRL) & ~irq_mask);
+       switch (vc4->gen) {
+       case VC4_GEN_4:
+               HVS_WRITE(SCALER_DISPCTRL,
+                         HVS_READ(SCALER_DISPCTRL) &
+                         ~SCALER_DISPCTRL_DSPEIEOF(channel));
+               break;
+
+       case VC4_GEN_5:
+               HVS_WRITE(SCALER_DISPCTRL,
+                         HVS_READ(SCALER_DISPCTRL) &
+                         ~SCALER5_DISPCTRL_DSPEIEOF(channel));
+               break;
+
+       default:
+               break;
+       }
 }
 
 static struct vc4_hvs_dlist_allocation *