/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
- /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
- * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
- * 10:G12A
+ /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
+ * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
+ * 10:G12A 11:G12B 12:SM1
*/
- ic_type = <10>;
+ ic_type = <12>;
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */
/* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/
interrupts = <0 57 1>;
interrupt-names = "hdmitx_hpd";
- /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
- * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
- * 10:G12A
+ /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM
+ * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD
+ * 10:G12A 11:G12B 12:SM1
*/
- ic_type = <10>;
+ ic_type = <12>;
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */
return hdmitx_hpd_hw_op_txlx(cmd);
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
+ case MESON_CPU_ID_SM1:
return hdmitx_hpd_hw_op_g12a(cmd);
default:
break;
case MESON_CPU_ID_TXLX:
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
+ case MESON_CPU_ID_SM1:
return read_hpd_gpio_txlx();
default:
break;
case MESON_CPU_ID_TXLX:
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
+ case MESON_CPU_ID_SM1:
return hdmitx_ddc_hw_op_txlx(cmd);
default:
break;
case MESON_CPU_ID_TXLX:
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
+ case MESON_CPU_ID_SM1:
ret = hdmitx_get_format_txlx();
break;
case MESON_CPU_ID_GXBB:
case MESON_CPU_ID_TXLX:
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
+ case MESON_CPU_ID_SM1:
hdmitx_sys_reset_txlx();
break;
case MESON_CPU_ID_GXBB:
switch (hdev->chip_type) {
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
+ case MESON_CPU_ID_SM1:
switch (mode) {
case 1: /* 5.94/4.5/3.7Gbps */
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb65c4);
switch (hdev->chip_type) {
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
+ case MESON_CPU_ID_SM1:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 1, 29, 1);
udelay(50);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0, 28, 1);
switch (hdev->chip_type) {
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
+ case MESON_CPU_ID_SM1:
for (i = 0; i < 4; i++) {
hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x0390000f);
hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x0390000e);
/* intr_maskn: MASK_N, one bit per interrupt source.
* 1=Enable interrupt source; 0=Disable interrupt source. Default 0.
+ * [ 8] hdcp_topology_err
+ * [ 7] rxsense_fall
+ * [ 6] rxsense_rise
+ * [ 5] err_i2c_timeout
* [ 4] hdcp22_rndnum_err
* [ 3] nonce_rfrsh_rise
* [ 2] hpd_fall_intr
#define HDMITX_TOP_I2C_BUSY_CNT_STAT (TOP_OFFSET_MASK + 0x029)
#define HDMITX_TOP_HDCP22_BSOD (TOP_SEC_OFFSET_MASK + 0x02A)
#define HDMITX_TOP_DDC_CNTL (TOP_OFFSET_MASK + 0x02B)
+#define HDMITX_TOP_DISABLE_NULL (TOP_OFFSET_MASK + 0x030)
#define HDMITX_TOP_REVOCMEM_ADDR_S (TOP_OFFSET_MASK + 0x2000 >> 2)
#define HDMITX_TOP_REVOCMEM_ADDR_E (TOP_OFFSET_MASK + 0x365E >> 2)
/* [ 1] Rsvd for read-only ksv_mem_access */
/* [ 0] ksv_mem_request */
#define HDMITX_DWC_A_KSVMEMCTRL (DWC_OFFSET_MASK + 0x5016)
+#define HDMITX_DWC_A_BSTATUS_HI (DWC_OFFSET_MASK + 0x5017)
+#define HDMITX_DWC_A_BSTATUS_LO (DWC_OFFSET_MASK + 0x5018)
#define HDMITX_DWC_HDCP_BSTATUS_0 (TOP_OFFSET_MASK + 0x2000)
#define HDMITX_DWC_HDCP_BSTATUS_1 (TOP_OFFSET_MASK + 0x2001)
case MESON_CPU_ID_GXM:
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
+ case MESON_CPU_ID_SM1:
default:
hd_write_reg(P_HHI_HDCP22_CLK_CNTL, 0x01000100);
break;
break;
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
+ case MESON_CPU_ID_SM1:
set_g12a_hpll_clk_out(frac_rate, clk);
break;
default:
switch (hdev->chip_type) {
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
+ case MESON_CPU_ID_SM1:
set_hpll_sspll_g12a(vic);
break;
case MESON_CPU_ID_GXBB:
break;
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
+ case MESON_CPU_ID_SM1:
set_hpll_od1_g12a(div);
break;
default:
break;
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
+ case MESON_CPU_ID_SM1:
set_hpll_od2_g12a(div);
break;
default:
break;
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
+ case MESON_CPU_ID_SM1:
set_hpll_od3_g12a(div);
break;
default:
switch (type) {
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
+ case MESON_CPU_ID_SM1:
map = reg_maps_g12a;
for (i = 0; i < REG_IDX_END; i++) {
map[i].p = ioremap(map[i].phy_addr, map[i].size);
case MESON_CPU_ID_GXM:
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
+ case MESON_CPU_ID_SM1:
default:
val = readl(TO_PMAP_ADDR(addr));
break;
case MESON_CPU_ID_GXM:
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
+ case MESON_CPU_ID_SM1:
default:
writel(val, TO_PMAP_ADDR(addr));
break;
#define MESON_CPU_ID_TXHD 9
#define MESON_CPU_ID_G12A 10
#define MESON_CPU_ID_G12B 11
+#define MESON_CPU_ID_SM1 12
/*****************************