Imm->getAPIntValue().isIntN(32))
return false;
+ // If this really a zext_inreg that can be represented with a movzx
+ // instruction, prefer that.
+ // TODO: We could shrink the load and fold if it is non-volatile.
+ if (U->getOpcode() == ISD::AND &&
+ (Imm->getAPIntValue() == UINT8_MAX ||
+ Imm->getAPIntValue() == UINT16_MAX ||
+ Imm->getAPIntValue() == UINT32_MAX))
+ return false;
+
// ADD/SUB with can negate the immediate and use the opposite operation
// to fit 128 into a sign extended 8 bit immediate.
if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB) &&
define i32 @main() nounwind {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movl $255, %eax
-; CHECK-NEXT: andl g_407, %eax
+; CHECK-NEXT: movl g_407, %eax
+; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: calll func_45
; CHECK-NEXT: addl $4, %esp
; CHECK-LABEL: t1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: movl $255, %ecx
-; CHECK-NEXT: andl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: movzbl %cl, %ecx
; CHECK-NEXT: movl (%eax,%ecx,4), %eax
; CHECK-NEXT: retl
; CHECK-LABEL: t2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: movl $65535, %ecx # imm = 0xFFFF
-; CHECK-NEXT: andl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: movzwl %cx, %ecx
; CHECK-NEXT: movl (%eax,%ecx,4), %eax
; CHECK-NEXT: retl