#define MARUCAM_CMD_INIT 0x00\r
#define MARUCAM_CMD_OPEN 0x04\r
#define MARUCAM_CMD_CLOSE 0x08\r
-#define MARUCAM_CMD_ISSTREAM 0x0C\r
+#define MARUCAM_CMD_ISR 0x0C\r
#define MARUCAM_CMD_START_PREVIEW 0x10\r
#define MARUCAM_CMD_STOP_PREVIEW 0x14\r
#define MARUCAM_CMD_S_PARAM 0x18\r
#define MARUCAM_CMD_ENUM_FINTV 0x40\r
#define MARUCAM_CMD_S_DATA 0x44\r
#define MARUCAM_CMD_G_DATA 0x48\r
-#define MARUCAM_CMD_CLRIRQ 0x4C\r
#define MARUCAM_CMD_DATACLR 0x50\r
#define MARUCAM_CMD_REQFRAME 0x54\r
\r
QemuCond thread_cond;\r
\r
void *vaddr; /* vram ptr */\r
+ uint32_t isr;\r
uint32_t streamon;\r
uint32_t buf_size;\r
uint32_t req_frame;\r
MaruCamState *state = (MaruCamState*)opaque;\r
\r
switch (offset & 0xFF) {\r
- case MARUCAM_CMD_ISSTREAM:\r
+ case MARUCAM_CMD_ISR:\r
qemu_mutex_lock(&state->thread_mutex);\r
- ret = state->streamon;\r
+ ret = state->isr;\r
+ state->isr = 0;\r
+ qemu_irq_lower(state->dev.irq[2]);\r
qemu_mutex_unlock(&state->thread_mutex);\r
break;\r
case MARUCAM_CMD_G_DATA:\r
break;\r
case MARUCAM_CMD_STOP_PREVIEW:\r
marucam_device_stop_preview(state);\r
+ memset(state->vaddr, 0, MARUCAM_MEM_SIZE);\r
break;\r
case MARUCAM_CMD_S_PARAM:\r
marucam_device_s_param(state);\r
case MARUCAM_CMD_DATACLR:\r
memset(state->param, 0, sizeof(MaruCamParam));\r
break;\r
- case MARUCAM_CMD_CLRIRQ:\r
- qemu_irq_lower(state->dev.irq[2]);\r
- break;\r
case MARUCAM_CMD_REQFRAME:\r
qemu_mutex_lock(&state->thread_mutex);\r
state->req_frame = value + 1;\r
\r
memory_region_init_ram(&s->vram, NULL, "marucamera.ram", MARUCAM_MEM_SIZE);\r
s->vaddr = memory_region_get_ram_ptr(&s->vram);\r
+ memset(s->vaddr, 0, MARUCAM_MEM_SIZE);\r
\r
memory_region_init_io (&s->mmio, &maru_camera_mmio_ops, s, "maru-camera-mmio", MARUCAM_REG_SIZE);\r
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);\r
\r
static int v4l2_fd;\r
static int convert_trial;\r
+static int ready_count;\r
\r
static struct v4l2_format dst_fmt;\r
\r
\r
qemu_mutex_lock(&state->thread_mutex);\r
if (state->streamon) {\r
- if (state->req_frame) {\r
- qemu_irq_raise(state->dev.irq[2]);\r
- state->req_frame = 0;\r
+ if (ready_count >= 4) {\r
+ if (state->req_frame) {\r
+ state->req_frame = 0; // clear request\r
+ state->isr |= 0x01; // set a flag of rasing a interrupt.\r
+ qemu_irq_raise(state->dev.irq[2]);\r
+ }\r
+ ret = 1;\r
+ } else {\r
+ ++ready_count; // skip a frame cause first some frame are distorted.\r
+ ret = 0;\r
}\r
- ret = 1;\r
} else {\r
ret = -1;\r
}\r
{\r
qemu_mutex_lock(&state->thread_mutex);\r
state->streamon = 1;\r
+ ready_count = 0;\r
state->buf_size = dst_fmt.fmt.pix.sizeimage;\r
qemu_cond_signal(&state->thread_cond);\r
qemu_mutex_unlock(&state->thread_mutex);\r
\r
static MaruCamState *g_state = NULL;\r
\r
+static uint32_t ready_count = 0;\r
static uint32_t cur_fmt_idx = 0;\r
static uint32_t cur_frame_idx = 0;\r
\r
}\r
index = !index;\r
\r
- if (g_state->req_frame) {\r
- mloop_evcmd_raise_intr(g_state->dev.irq[2]);\r
- g_state->req_frame = 0;\r
+ qemu_mutex_lock(&g_state->thread_mutex);\r
+ if (ready_count >= 4) {\r
+ if (g_state->req_frame) {\r
+ g_state->req_frame = 0; // clear request\r
+ g_state->isr |= 0x01; // set a flag raising a interrupt.\r
+ mloop_evcmd_raise_intr(g_state->dev.irq[2]);\r
+ }\r
+ } else {\r
+ ++ready_count; // skip a frame cause first some frame are distorted.\r
}\r
+ qemu_mutex_unlock(&g_state->thread_mutex);\r
return S_OK;\r
}\r
\r
\r
qemu_mutex_lock(&state->thread_mutex);\r
state->streamon = 1;\r
+ ready_count = 0;\r
qemu_mutex_unlock(&state->thread_mutex);\r
\r
width = supported_dst_frames[cur_frame_idx].width;\r