riscv: dts: starfive: Add cpu scaling for JH7110 SoC

Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC.
It supports up to 4 cpu frequency loads.

Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
[Backported patch : https://lore.kernel.org/all/20230421031431.23010-4-mason.huo@starfivetech.com/]
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Change-Id: I0aeac76676938da45165a460a1d042fc36d2c8e4

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index eed8777..9937b08 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -405,3 +405,19 @@
                dr_mode = "peripheral";
        };
 };
+
+&U74_1 {
+       cpu-supply = <&vdd_cpu>;
+};
+
+&U74_2 {
+       cpu-supply = <&vdd_cpu>;
+};
+
+&U74_3 {
+       cpu-supply = <&vdd_cpu>;
+};
+
+&U74_4 {
+       cpu-supply = <&vdd_cpu>;
+};

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index fdb1efd..c10e8ee 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -63,6 +63,9 @@
                        next-level-cache = <&ccache>;
                        riscv,isa = "rv64imafdc_zba_zbb";
                        tlb-split;
+                       operating-points-v2 = <&cpu_opp>;
+                       clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+                       clock-names = "cpu";
 
                        cpu1_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -89,6 +92,9 @@
                        next-level-cache = <&ccache>;
                        riscv,isa = "rv64imafdc_zba_zbb";
                        tlb-split;
+                       operating-points-v2 = <&cpu_opp>;
+                       clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+                       clock-names = "cpu";
 
                        cpu2_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -115,6 +121,9 @@
                        next-level-cache = <&ccache>;
                        riscv,isa = "rv64imafdc_zba_zbb";
                        tlb-split;
+                       operating-points-v2 = <&cpu_opp>;
+                       clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+                       clock-names = "cpu";
 
                        cpu3_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -141,6 +150,9 @@
                        next-level-cache = <&ccache>;
                        riscv,isa = "rv64imafdc_zba_zbb";
                        tlb-split;
+                       operating-points-v2 = <&cpu_opp>;
+                       clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+                       clock-names = "cpu";
 
                        cpu4_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -174,6 +186,27 @@
                };
        };
 
+       cpu_opp: opp-table-0 {
+                       compatible = "operating-points-v2";
+                       opp-shared;
+                       opp-375000000 {
+                                       opp-hz = /bits/ 64 <375000000>;
+                                       opp-microvolt = <800000>;
+                       };
+                       opp-500000000 {
+                                       opp-hz = /bits/ 64 <500000000>;
+                                       opp-microvolt = <800000>;
+                       };
+                       opp-750000000 {
+                                       opp-hz = /bits/ 64 <750000000>;
+                                       opp-microvolt = <800000>;
+                       };
+                       opp-1500000000 {
+                                       opp-hz = /bits/ 64 <1500000000>;
+                                       opp-microvolt = <1040000>;
+                       };
+       };
+
        dvp_clk: dvp-clock {
                compatible = "fixed-clock";
                clock-output-names = "dvp_clk";