Improve Backend comment. (#18567)

Summary:
Pull Request resolved: https://github.com/pytorch/pytorch/pull/18567
ghimport-source-id: 1e50e611a3afcfae86828b7afe06c3fdc6a7bef7

Stack from [ghstack](https://github.com/ezyang/ghstack):
* **#18567 Improve Backend comment.**

Signed-off-by: Edward Z. Yang <ezyang@fb.com>
Reviewed By: dzhulgakov

Differential Revision: D14666189

fbshipit-source-id: 64a41c4a998b1a59ff780d1ae06fa16e5ef3c7c4

diff --git a/c10/core/Backend.h b/c10/core/Backend.h
index 0e1e1fa..3a3c6c8 100644 (file)
--- a/c10/core/Backend.h
+++ b/c10/core/Backend.h
@@ -10,15 +10,21 @@
 namespace c10 {
 
 /**
- * This legacy enum class defines the set of backends supported by
- * old school, code generated Type-based ATen.  The reason we are
- * sunsetting this enum class is because it doesn't allow for
- * open registration of backends.  TensorTypeId is the replacement
- * for Backend which supports open registration.
+ * This legacy enum class defines the set of backends supported by old school,
+ * code generated Type-based ATen.  A "backend" in this sense roughly
+ * corresponds to the cartesian product of (device type, layout), but restricted
+ * only to combinations which we actually have kernels for.  Backend does NOT
+ * include dtype.
  *
- * ARE YOU SURE YOU WANT TO USE THIS TYPE?  Think about if SparseCPU/SparseCUDA
- * would make sense in your use case.  If it doesn't make sense, maybe
- * you want DeviceType.
+ * The reason we are sunsetting this enum class is because it doesn't allow for
+ * open registration; e.g., if you want to add SparseXLA, you'd have to
+ * edit this enum; you wouldn't be able to do it out of tree.  TensorTypeId is
+ * the replacement for Backend which supports open registration.
+ *
+ * NB: The concept of 'Backend' here disagrees with the notion of backend
+ * exposed to users in torch.backends.  Backend here is something like "CPU"
+ * or "SparseCUDA"; backend in torch.backends is something like "MKL" or
+ * "CUDNN".
  */
 enum class Backend { CPU, CUDA, HIP, SparseCPU, SparseCUDA, SparseHIP, MSNPU, XLA, Undefined, NumOptions };