clk: uniphier: Add SCSSI clock gate for each channel

[ Upstream commit 1ec09a2ec67a0baa46a3ccac041dbcdbc6db2cb9 ]

SCSSI has clock gates for each channel in the SoCs newer than Pro4,
so this adds missing clock gates for channel 1, 2 and 3. And more, this
moves MCSSI clock ID after SCSSI.

Fixes: ff388ee36516 ("clk: uniphier: add clock frequency support for SPI")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Link: https://lkml.kernel.org/r/1577410925-22021-1-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/uniphier/clk-uniphier-peri.c b/drivers/clk/uniphier/clk-uniphier-peri.c
index 89b3ac3..8b75dc1 100644 (file)
--- a/drivers/clk/uniphier/clk-uniphier-peri.c
+++ b/drivers/clk/uniphier/clk-uniphier-peri.c
@@ -27,8 +27,8 @@
 #define UNIPHIER_PERI_CLK_FI2C(idx, ch)                                        \
        UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c", 0x24, 24 + (ch))
 
-#define UNIPHIER_PERI_CLK_SCSSI(idx)                                   \
-       UNIPHIER_CLK_GATE("scssi", (idx), "spi", 0x20, 17)
+#define UNIPHIER_PERI_CLK_SCSSI(idx, ch)                               \
+       UNIPHIER_CLK_GATE("scssi" #ch, (idx), "spi", 0x20, 17 + (ch))
 
 #define UNIPHIER_PERI_CLK_MCSSI(idx)                                   \
        UNIPHIER_CLK_GATE("mcssi", (idx), "spi", 0x24, 14)
@@ -44,7 +44,7 @@ const struct uniphier_clk_data uniphier_ld4_peri_clk_data[] = {
        UNIPHIER_PERI_CLK_I2C(6, 2),
        UNIPHIER_PERI_CLK_I2C(7, 3),
        UNIPHIER_PERI_CLK_I2C(8, 4),
-       UNIPHIER_PERI_CLK_SCSSI(11),
+       UNIPHIER_PERI_CLK_SCSSI(11, 0),
        { /* sentinel */ }
 };
 
@@ -60,7 +60,10 @@ const struct uniphier_clk_data uniphier_pro4_peri_clk_data[] = {
        UNIPHIER_PERI_CLK_FI2C(8, 4),
        UNIPHIER_PERI_CLK_FI2C(9, 5),
        UNIPHIER_PERI_CLK_FI2C(10, 6),
-       UNIPHIER_PERI_CLK_SCSSI(11),
-       UNIPHIER_PERI_CLK_MCSSI(12),
+       UNIPHIER_PERI_CLK_SCSSI(11, 0),
+       UNIPHIER_PERI_CLK_SCSSI(12, 1),
+       UNIPHIER_PERI_CLK_SCSSI(13, 2),
+       UNIPHIER_PERI_CLK_SCSSI(14, 3),
+       UNIPHIER_PERI_CLK_MCSSI(15),
        { /* sentinel */ }
 };