SDValue Op0 = Op.getOperand(0);
EVT Op0VT = Op0.getValueType();
MVT XLenVT = Subtarget.getXLenVT();
+ if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) {
+ SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Op0);
+ SDValue FPConv = DAG.getNode(RISCVISD::FMV_H_X, DL, MVT::f16, NewOp0);
+ return FPConv;
+ }
+ if (VT == MVT::f32 && Op0VT == MVT::i32 && Subtarget.is64Bit() &&
+ Subtarget.hasStdExtF()) {
+ SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
+ SDValue FPConv =
+ DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, NewOp0);
+ return FPConv;
+ }
+
+ // Consider other scalar<->scalar casts as legal if the types are legal.
+ // Otherwise expand them.
+ if (!VT.isVector() && !Op0VT.isVector()) {
+ if (isTypeLegal(VT) && isTypeLegal(Op0VT))
+ return Op;
+ return SDValue();
+ }
+
+ assert(!VT.isScalableVector() && !Op0VT.isScalableVector() &&
+ "Unexpected types");
+
if (VT.isFixedLengthVector()) {
// We can handle fixed length vector bitcasts with a simple replacement
// in isel.
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, BVec,
DAG.getConstant(0, DL, XLenVT));
}
- if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) {
- SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Op0);
- SDValue FPConv = DAG.getNode(RISCVISD::FMV_H_X, DL, MVT::f16, NewOp0);
- return FPConv;
- }
- if (VT == MVT::f32 && Op0VT == MVT::i32 && Subtarget.is64Bit() &&
- Subtarget.hasStdExtF()) {
- SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
- SDValue FPConv =
- DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, NewOp0);
- return FPConv;
- }
return SDValue();
}
case ISD::INTRINSIC_WO_CHAIN:
;
; RV64ELEN32-LABEL: bitcast_v1i64_f64:
; RV64ELEN32: # %bb.0:
-; RV64ELEN32-NEXT: addi sp, sp, -16
-; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16
-; RV64ELEN32-NEXT: sd a0, 8(sp)
-; RV64ELEN32-NEXT: fld fa0, 8(sp)
-; RV64ELEN32-NEXT: addi sp, sp, 16
+; RV64ELEN32-NEXT: fmv.d.x fa0, a0
; RV64ELEN32-NEXT: ret
%b = bitcast <1 x i64> %a to double
ret double %b