COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o
COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
-COBJS-$(CONFIG_S5PC1XXFB) += s5p-fb.o s5pc100_fimd.o tl2796.o
+COBJS-$(CONFIG_S5PC1XXFB) += s5p-fb.o s5p-fimd.o tl2796.o
#COBJS-$(CONFIG_SUBLCD) += eltz_lcd.o
COBJS-y += videomodes.o
/*
- * S5PC100 LCD Controller driver.
+ * S5PC100 and S5PC110 LCD Controller driver.
*
* Author: InKi Dae <inki.dae@samsung.com>
*
#include <stdarg.h>
#include <linux/types.h>
#include <asm/io.h>
+#include <asm/arch/cpu.h>
#include <lcd.h>
-#include "s5pcfb.h"
+#include "s5p-fb.h"
#include "opening_wvga_32.h"
#define PANEL_WIDTH 480
.vl_bpix = S5P_LCD_BPP,
.vl_lbw = 0,
.vl_splt = 0,
- .vl_clor = 0,
+ .vl_clor = 1,
.vl_tft = 1,
.vl_hpw = 4,
.vl_efw = 8,
};
-static void s5pc_lcd_clock_enable(void)
-{
- s5pc_fimd_lcd_clock_enable();
-}
-
static void s5pc_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
{
unsigned long palette_size, palette_mem_size;
static void s5pc_gpio_setup(void)
{
- s5pc_fimd_gpio_setup();
+ if (cpu_is_s5pc100())
+ s5pc_c100_gpio_setup();
+ else
+ s5pc_c110_gpio_setup();
}
static void s5pc_lcd_init(vidinfo_t *vid)
static void lcd_panel_on(void)
{
- tl2796_panel_init();
- tl2796_panel_power_on();
+ if (cpu_is_s5pc100()) {
+ tl2796_c100_panel_init();
+ tl2796_c100_panel_power_on();
+ } else {
+ tl2796_c110_panel_init();
+ tl2796_c110_panel_power_on();
+ }
+
tl2796_panel_enable();
}
void lcd_ctrl_init(void *lcdbase)
{
- s5pc_lcd_clock_enable();
-
s5pc_lcd_init_mem(lcdbase, &panel_info);
#if defined(CONFIG_S5PC1XXFB_TEST)
}s5pcfb_fimd_info_t;
-void s5pc_fimd_lcd_clock_enable(void);
+enum s5pcfb_rgb_mode_t {
+ MODE_RGB_P = 0,
+ MODE_BGR_P = 1,
+ MODE_RGB_S = 2,
+ MODE_BGR_S = 3,
+};
+
void s5pc_fimd_lcd_init_mem(unsigned long screen_base, unsigned long fb_size,
unsigned long palette_size);
void s5pc_fimd_lcd_init(vidinfo_t *vid);
unsigned long s5pc_fimd_calc_fbsize(void);
-void s5pc_fimd_gpio_setup(void);
+void s5pc_c100_gpio_setup(void);
+void s5pc_c110_gpio_setup(void);
+
+void tl2796_c100_panel_init(void);
+void tl2796_c100_panel_power_on(void);
+void tl2796_c110_panel_init(void);
+void tl2796_c110_panel_power_on(void);
+
#endif
--- /dev/null
+/*
+ * S5PC100 and S5PC110 LCD Controller Specific driver.
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <stdarg.h>
+#include <linux/types.h>
+#include <asm/io.h>
+#include <lcd.h>
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/regs-fb.h>
+#include <asm/arch/hardware.h>
+#include "s5p-fb.h"
+
+#define MPLL 1
+
+/* LCD Panel definitions */
+#define PANEL_WIDTH 480
+#define PANEL_HEIGHT 800
+#define S5P_LCD_BPP 32
+
+#define S5PCFB_VBPE 1
+
+#define S5PCFB_VFPE 1
+
+#define S5PCFB_HRES 480
+#define S5PCFB_VRES 800
+
+#define S5PCFB_HRES_VIRTUAL 480
+#define S5PCFB_VRES_VIRTUAL 800
+
+#define S5PCFB_HRES_OSD 480
+#define S5PCFB_VRES_OSD 800
+
+#define S5P_VFRAME_FREQ 60
+
+static unsigned int ctrl_base;
+static unsigned long *lcd_base_addr;
+
+extern unsigned long get_pll_clk(int pllreg);
+
+void s5pc_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, u_long palette_size)
+{
+ lcd_base_addr = (unsigned long *)screen_base;
+
+ udebug("lcd_base_addr(framebuffer memory) = %x\n", lcd_base_addr);
+
+ return;
+}
+
+void s5pc_c100_gpio_setup(void)
+{
+ /* set GPF0[0:7] for RGB Interface and Data lines */
+ writel(0x22222222, 0xE03000E0);
+
+ /* set Data lines */
+ writel(0x22222222, 0xE0300100);
+ writel(0x22222222, 0xE0300120);
+ writel(0x2222, 0xE0300140);
+
+ /* set gpio configuration pin for MLCD_RST */
+ writel(0x10000000, 0xE0300C20);
+
+ /* set gpio configuration pin for MLCD_ON */
+ writel(0x1000, 0xE0300220);
+ writel(readl(0xE0300224) & 0xf7, 0xE0300224);
+
+ /* set gpio configuration pin for DISPLAY_CS, DISPLAY_CLK and DISPLSY_SI */
+ writel(0x11100000, 0xE0300300);
+}
+
+void s5pc_c110_gpio_setup(void)
+{
+ /* set GPF0[0:7] for RGB Interface and Data lines */
+ writel(0x22222222, 0xE0200120);
+ /* pull-up/down disable */
+ writel(0x0, 0xE0200128);
+ /* drive strength to max */
+ writel(0xffffffff, 0xE020012C);
+
+ /* set Data lines */
+ writel(0x22222222, 0xE0200140);
+ writel(0x22222222, 0xE0200160);
+ writel(0x2222, 0xE0200180);
+
+ /* drive strength to max */
+ writel(0xffffffff, 0xE020014C);
+ writel(0xffffffff, 0xE020016C);
+ writel(0x000000ff, 0xE020018C);
+
+ /* pull-up/down disable */
+ writel(0x0, 0xE0200148);
+ writel(0x0, 0xE0200168);
+ writel(0x0, 0xE0200188);
+
+ /* display output path selection */
+ writel(0x2, 0xE0107008);
+
+ /* set gpio configuration pin for MLCD_RST */
+ writel(0x10000000, 0xE0200C20);
+
+ /* set gpio configuration pin for MLCD_ON */
+ writel(0x1000, 0xE0200260);
+ writel(readl(0xE0200264) & 0xf7, 0xE0200264);
+
+ /* set gpio configuration pin for DISPLAY_CS, DISPLAY_CLK, DISPLSY_SI and LCD_ID */
+ writel(0x10, 0xE02002E0);
+ writel(0x1110, 0xE0200340);
+
+ return;
+}
+
+static void s5pc_fimd_set_par(unsigned int win_id)
+{
+ unsigned int cfg = 0;
+
+ /* set window control */
+ cfg = readl(ctrl_base + S5P_WINCON(win_id));
+
+ cfg &= ~(S5P_WINCON_BITSWP_ENABLE | S5P_WINCON_BYTESWP_ENABLE | \
+ S5P_WINCON_HAWSWP_ENABLE | S5P_WINCON_WSWP_ENABLE | \
+ S5P_WINCON_BURSTLEN_MASK | S5P_WINCON_BPPMODE_MASK | \
+ S5P_WINCON_INRGB_MASK | S5P_WINCON_DATAPATH_MASK);
+
+ /* DATAPATH is DMA */
+ cfg |= S5P_WINCON_DATAPATH_DMA;
+
+ /* bpp is 32 */
+ cfg |= S5P_WINCON_WSWP_ENABLE;
+
+ /* dma burst is 16 */
+ cfg |= S5P_WINCON_BURSTLEN_16WORD;
+
+ /* pixel format is unpacked RGB888 */
+ cfg |= S5P_WINCON_BPPMODE_24BPP_888;
+
+ writel(cfg, ctrl_base + S5P_WINCON(win_id));
+ udebug("wincon%d = %x\n", win_id, cfg);
+
+ /* set window position to x=0, y=0*/
+ cfg = S5P_VIDOSD_LEFT_X(0) | S5P_VIDOSD_TOP_Y(0);
+ writel(cfg, ctrl_base + S5P_VIDOSD_A(win_id));
+ udebug("window postion left,top = %x\n", cfg);
+
+ cfg = S5P_VIDOSD_RIGHT_X(PANEL_WIDTH - 1) |
+ S5P_VIDOSD_BOTTOM_Y(PANEL_HEIGHT - 1);
+ writel(cfg, ctrl_base + S5P_VIDOSD_B(win_id));
+ udebug("window postion right,bottom= %x\n", cfg);
+
+ /* set window size for window0*/
+ cfg = S5P_VIDOSD_SIZE(PANEL_WIDTH * PANEL_HEIGHT);
+ writel(cfg, ctrl_base + S5P_VIDOSD_C(win_id));
+ udebug("vidosd_c%d= %x\n", win_id, cfg);
+
+ return;
+}
+
+static void s5pc_fimd_set_buffer_address(unsigned int win_id)
+{
+ unsigned long start_addr, end_addr;
+
+ start_addr = (unsigned long)lcd_base_addr;
+ end_addr = start_addr + ((PANEL_WIDTH * (S5P_LCD_BPP / 8))
+ * PANEL_HEIGHT);
+
+ writel(start_addr, ctrl_base + S5P_VIDADDR_START0(win_id));
+ writel(end_addr, ctrl_base + S5P_VIDADDR_END0(win_id));
+
+ udebug("start addr = %x, end addr = %x\n", start_addr, end_addr);
+
+ return;
+}
+
+static void s5pc_fimd_set_clock(vidinfo_t *vid)
+{
+ unsigned int cfg = 0, div = 0, mpll_ratio = 0;
+ unsigned long pixel_clock, src_clock, max_clock;
+
+ max_clock = 66 * 1000000;
+
+ pixel_clock = S5P_VFRAME_FREQ * (vid->vl_hpw + vid->vl_blw + vid->vl_elw + vid->vl_width) *
+ (vid->vl_vpw + vid->vl_bfw + vid->vl_efw + vid->vl_height);
+
+ src_clock = get_pll_clk(MPLL);
+
+ cfg = readl(ctrl_base + S5P_VIDCON0);
+ cfg &= ~(S5P_VIDCON0_CLKSEL_MASK | S5P_VIDCON0_CLKVALUP_MASK | \
+ S5P_VIDCON0_VCLKEN_MASK | S5P_VIDCON0_CLKDIR_MASK);
+ cfg |= (S5P_VIDCON0_CLKSEL_HCLK | S5P_VIDCON0_CLKVALUP_ALWAYS | \
+ S5P_VIDCON0_VCLKEN_NORMAL | S5P_VIDCON0_CLKDIR_DIVIDED);
+
+ if (pixel_clock > max_clock)
+ pixel_clock = max_clock;
+
+ /* get mpll ratio */
+ if (cpu_is_s5pc110())
+ mpll_ratio = (readl(0xE0100300) & 0xf0000) >> 16;
+ else
+ mpll_ratio = (readl(0xE0100304) & 0xf0) >> 4;
+
+ /*
+ * It can get sorce clock speed as (mpll / mpll_ratio)
+ * because lcd controller uses hclk_dsys.
+ * mpll is a parent of hclk_dsys.
+ */
+ div = (unsigned int)((src_clock / (mpll_ratio + 1)) / pixel_clock);
+ cfg |= S5P_VIDCON0_CLKVAL_F(div - 1);
+ writel(cfg, ctrl_base + S5P_VIDCON0);
+
+ udebug("mpll_ratio = %d, src_clock = %d, pixel_clock = %d, div = %d\n",
+ mpll_ratio, src_clock, pixel_clock, div);
+
+ return;
+}
+
+void s5pc_fimd_lcd_init(vidinfo_t *vid)
+{
+ unsigned int cfg = 0, rgb_mode, win_id = 0;
+
+ /* select register base according to cpu type */
+ if (cpu_is_s5pc110())
+ ctrl_base = 0xF8000000;
+ else
+ ctrl_base = 0xEE000000;
+
+ /* set output to RGB */
+ rgb_mode = MODE_RGB_P;
+ cfg = readl(ctrl_base + S5P_VIDCON0);
+ cfg &= ~S5P_VIDCON0_VIDOUT_MASK;
+
+ /* clock source is HCLK */
+ cfg |= 0 << 2;
+
+ cfg |= S5P_VIDCON0_VIDOUT_RGB;
+ writel(cfg, ctrl_base + S5P_VIDCON0);
+
+ /* set display mode */
+ cfg = readl(ctrl_base + S5P_VIDCON0);
+ cfg &= ~S5P_VIDCON0_PNRMODE_MASK;
+ cfg |= (rgb_mode << S5P_VIDCON0_PNRMODE_SHIFT);
+ writel(cfg, ctrl_base + S5P_VIDCON0);
+
+ /* set polarity */
+ cfg = 0;
+ cfg |= S5P_VIDCON1_IVDEN_INVERT | S5P_VIDCON1_IVCLK_RISING_EDGE;
+ writel(cfg, ctrl_base + S5P_VIDCON1);
+
+
+ /* set timing */
+ cfg = 0;
+ //cfg |= S5P_VIDTCON0_VBPDE(S5PCFB_VBPE - 1);
+ cfg |= S5P_VIDTCON0_VBPD(vid->vl_bfw - 1);
+ cfg |= S5P_VIDTCON0_VFPD(vid->vl_efw - 1);
+ cfg |= S5P_VIDTCON0_VSPW(vid->vl_vpw - 1);
+ writel(cfg, ctrl_base + S5P_VIDTCON0);
+ udebug("vidtcon0 = %x\n", cfg);
+
+ cfg = 0;
+ //cfg |= S5P_VIDTCON1_VFPDE(S5PCFB_VFPE - 1);
+ cfg |= S5P_VIDTCON1_HBPD(vid->vl_blw - 1);
+ cfg |= S5P_VIDTCON1_HFPD(vid->vl_elw - 1);
+ cfg |= S5P_VIDTCON1_HSPW(vid->vl_hpw - 1);
+
+ writel(cfg, ctrl_base + S5P_VIDTCON1);
+ udebug("vidtcon1 = %x\n", cfg);
+
+ /* set lcd size */
+ cfg = 0;
+ cfg |= S5P_VIDTCON2_HOZVAL(PANEL_WIDTH - 1);
+ cfg |= S5P_VIDTCON2_LINEVAL(PANEL_HEIGHT - 1);
+
+ writel(cfg, ctrl_base + S5P_VIDTCON2);
+ udebug("vidtcon2 = %x\n", cfg);
+
+ /* set par */
+ s5pc_fimd_set_par(win_id);
+
+ /* set memory address */
+ s5pc_fimd_set_buffer_address(win_id);
+
+ /* set buffer size */
+ cfg = S5P_VIDADDR_PAGEWIDTH(PANEL_WIDTH * S5P_LCD_BPP / 8);
+ writel(cfg, ctrl_base + S5P_VIDADDR_SIZE(win_id));
+ udebug("vidaddr_pagewidth = %d\n", cfg);
+
+ /* set clock */
+ s5pc_fimd_set_clock(vid);
+
+ /* display on */
+ cfg = readl(ctrl_base + S5P_VIDCON0);
+ cfg |= (S5P_VIDCON0_ENVID_ENABLE | S5P_VIDCON0_ENVID_F_ENABLE);
+ writel(cfg, ctrl_base + S5P_VIDCON0);
+ udebug("vidcon0 = %x\n", cfg);
+
+ /* enable window */
+ cfg = readl(ctrl_base + S5P_WINCON(win_id));
+ cfg |= S5P_WINCON_ENWIN_ENABLE;
+ writel(cfg, ctrl_base + S5P_WINCON(win_id));
+ udebug("wincon%d=%x\n", win_id, cfg);
+
+ udebug("lcd controller init completed.\n");
+
+ return;
+}
+
+ulong s5pc_fimd_calc_fbsize(void)
+{
+ return (PANEL_WIDTH * PANEL_HEIGHT * (S5P_LCD_BPP / 8));
+}
+++ /dev/null
-/*
- * S5PC100 LCD Controller Specific driver.
- *
- * Author: InKi Dae <inki.dae@samsung.com>
- */
-
-#include <config.h>
-#include <common.h>
-#include <stdarg.h>
-#include <linux/types.h>
-#include <asm/io.h>
-#include <lcd.h>
-
-#include <asm/arch/regs-lcd.h>
-#include <asm/arch/hardware.h>
-#include "s5pcfb.h"
-
-#define MPLL 1
-
-/* clock definitions */
-#define SELECT_CLOCK_SOURCE2 0xE0100208
-#define LCD_CLOCK_SOURCE 0x1000
-
-#define CLOCK_DIV1 0xE0100304
-
-/* LCD Panel definitions */
-#define PANEL_WIDTH 480
-#define PANEL_HEIGHT 800
-
-/* LCD Panel definitions */
-#define PANEL_WIDTH 480
-#define PANEL_HEIGHT 800
-#define S5P_LCD_BPP 32
-
-#define S5PCFB_HFP 8
-#define S5PCFB_HSW 4
-#define S5PCFB_HBP 8
-
-#define S5PCFB_VFP 8
-#define S5PCFB_VSW 4
-#define S5PCFB_VBP 8
-
-#define S5PCFB_HRES 480
-#define S5PCFB_VRES 800
-
-#define S5PCFB_HRES_VIRTUAL 480
-#define S5PCFB_VRES_VIRTUAL 800
-
-#define S5PCFB_HRES_OSD 480
-#define S5PCFB_VRES_OSD 800
-
-#define S5P_VFRAME_FREQ 60
-
-/* LCD Controller data */
-s5pcfb_fimd_info_t s5pcfb_fimd = {
- .vidcon0 = S5P_VIDCON0_INTERLACE_F_PROGRESSIVE | S5P_VIDCON0_VIDOUT_RGB_IF | \
- S5P_VIDCON0_L1_DATA16_SUB_16PLUS8_MODE | \
- S5P_VIDCON0_L0_DATA16_MAIN_16PLUS8_MODE | \
- S5P_VIDCON0_PNRMODE_RGB_P | S5P_VIDCON0_CLKVALUP_ALWAYS | \
- S5P_VIDCON0_CLKDIR_DIVIDED | S5P_VIDCON0_CLKSEL_F_HCLK | \
- S5P_VIDCON0_ENVID_DISABLE | S5P_VIDCON0_ENVID_F_DISABLE,
-
- .vidcon1 = S5P_VIDCON1_IHSYNC_NORMAL | S5P_VIDCON1_IVSYNC_NORMAL |
- S5P_VIDCON1_IVDEN_INVERT | S5P_VIDCON1_IVCLK_RISE_EDGE,
-
- .vidtcon0 = S5P_VIDTCON0_VBPD(S5PCFB_VBP - 1) | \
- S5P_VIDTCON0_VFPD(S5PCFB_VFP - 1) | \
- S5P_VIDTCON0_VSPW(S5PCFB_VSW - 1),
-
- .vidtcon1 = S5P_VIDTCON1_HBPD(S5PCFB_HBP - 1) | \
- S5P_VIDTCON1_HFPD(S5PCFB_HFP - 1) | \
- S5P_VIDTCON1_HSPW(S5PCFB_HSW - 1),
-
- .vidtcon2 = S5P_VIDTCON2_LINEVAL(S5PCFB_VRES - 1) | \
- S5P_VIDTCON2_HOZVAL(S5PCFB_HRES - 1),
-
- .vidosd0a = S5P_VIDOSDxA_OSD_LTX_F(0) | S5P_VIDOSDxA_OSD_LTY_F(0),
- .vidosd0b = S5P_VIDOSDxB_OSD_RBX_F(S5PCFB_HRES - 1) | \
- S5P_VIDOSDxB_OSD_RBY_F(S5PCFB_VRES - 1),
-
- .vidosd1a = S5P_VIDOSDxA_OSD_LTX_F(0) | S5P_VIDOSDxA_OSD_LTY_F(0),
- .vidosd1b = S5P_VIDOSDxB_OSD_RBX_F(S5PCFB_HRES_OSD - 1) | \
- S5P_VIDOSDxB_OSD_RBY_F(S5PCFB_VRES_OSD - 1),
-
- .width = PANEL_WIDTH,
- .height = PANEL_HEIGHT,
- .xres = PANEL_WIDTH,
- .yres = PANEL_HEIGHT,
-
- .dithmode = (S5P_DITHMODE_RDITHPOS_5BIT | S5P_DITHMODE_GDITHPOS_6BIT | \
- S5P_DITHMODE_BDITHPOS_5BIT ) & S5P_DITHMODE_DITHERING_DISABLE,
-
- .wincon0 = S5P_WINCONx_HAWSWP_DISABLE | S5P_WINCONx_BURSTLEN_16WORD | \
- S5P_WINCONx_BPPMODE_F_24BPP_888,
-
- .bpp = S5P_LCD_BPP,
- .bytes_per_pixel = 4,
- .wpalcon = S5P_WPALCON_W0PAL_24BIT,
-
- .vidintcon0 = S5P_VIDINTCON0_FRAMESEL0_VSYNC | S5P_VIDINTCON0_FRAMESEL1_NONE | \
- S5P_VIDINTCON0_INTFRMEN_DISABLE | S5P_VIDINTCON0_FIFOSEL_WIN0 | \
- S5P_VIDINTCON0_FIFOLEVEL_25 | S5P_VIDINTCON0_INTFIFOEN_DISABLE | \
- S5P_VIDINTCON0_INTEN_ENABLE,
- .vidintcon1 = 0,
- .xoffset = 0,
- .yoffset = 0,
-};
-
-extern unsigned long get_pll_clk(int pllreg);
-
-void s5pc_fimd_lcd_clock_enable(void)
-{
- __REG(SELECT_CLOCK_SOURCE2) = LCD_CLOCK_SOURCE;
-}
-
-void s5pc_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, u_long palette_size)
-{
- u_long palette_mem_size;
-
- s5pcfb_fimd.screen = screen_base;
-
- s5pcfb_fimd.palette_size = palette_size;
- palette_mem_size = palette_size * sizeof(u32);
-
- s5pcfb_fimd.palette = screen_base + fb_size + PAGE_SIZE - palette_mem_size;
-
- udebug("palette=%x\n", (unsigned int)s5pcfb_fimd.palette);
-}
-
-void s5pc_fimd_gpio_setup(void)
-{
- /* set GPF0[0:7] for RGB Interface and Data lines */
- writel(0x22222222, 0xE03000E0);
-
- /* set Data lines */
- writel(0x22222222, 0xE0300100);
- writel(0x22222222, 0xE0300120);
- writel(0x2222, 0xE0300140);
-
- /* set gpio configuration pin for MLCD_RST */
- writel(0x10000000, 0xE0300C20);
-
- /* set gpio configuration pin for MLCD_ON */
- writel(0x1000, 0xE0300220);
- writel(readl(0xE0300224) & 0xf7, 0xE0300224);
-
- /* set gpio configuration pin for DISPLAY_CS, DISPLAY_CLK and DISPLSY_SI */
- writel(0x11100000, 0xE0300300);
-}
-
-void s5pc_fimd_lcd_init(vidinfo_t *vid)
-{
- unsigned int mpll_ratio, offset, fb_size, page_width;
-
- s5pcfb_fimd.bytes_per_pixel = vid->vl_bpix / 8;
- page_width = s5pcfb_fimd.xres * s5pcfb_fimd.bytes_per_pixel;
- offset = 0;
-
- /* calculate LCD Pixel clock */
- s5pcfb_fimd.pixclock = (S5P_VFRAME_FREQ *
- (vid->vl_hpw + vid->vl_blw + vid->vl_elw + vid->vl_width) *
- (vid->vl_vpw + vid->vl_bfw + vid->vl_efw + vid->vl_height));
-
- /* initialize the fimd specific */
- s5pcfb_fimd.vidintcon0 &= ~S5P_VIDINTCON0_FRAMESEL0_MASK;
- s5pcfb_fimd.vidintcon0 |= S5P_VIDINTCON0_FRAMESEL0_VSYNC;
- s5pcfb_fimd.vidintcon0 |= S5P_VIDINTCON0_INTFRMEN_ENABLE;
-
- writel(s5pcfb_fimd.vidintcon0, S5P_VIDINTCON0);
-
- /* set configuration register for VCLK */
- s5pcfb_fimd.vidcon0 = s5pcfb_fimd.vidcon0 &
- ~(S5P_VIDCON0_ENVID_ENABLE | S5P_VIDCON0_ENVID_F_ENABLE);
- writel(s5pcfb_fimd.vidcon0, S5P_VIDCON0);
-
- mpll_ratio = (readl(CLOCK_DIV1) & 0x000000f0) >> 4;
- s5pcfb_fimd.vidcon0 |= S5P_VIDCON0_CLKVAL_F((int)(((get_pll_clk(MPLL) / mpll_ratio)
- / s5pcfb_fimd.pixclock) - 1));
-
- udebug("mpll_ratio = %d, MCLK = %d, pixclock=%d, vidcon0 = %d\n",
- mpll_ratio, (unsigned int)get_pll_clk(MPLL), (unsigned int)s5pcfb_fimd.pixclock,
- (unsigned int)s5pcfb_fimd.vidcon0);
-
- /* set window size */
- s5pcfb_fimd.vidosd0c = S5P_VIDOSD0C_OSDSIZE(PANEL_WIDTH * PANEL_HEIGHT);
-
- /* set wondow position */
- writel(S5P_VIDOSDxA_OSD_LTX_F(0) | S5P_VIDOSDxA_OSD_LTY_F(0), S5P_VIDOSD0A);
- writel(S5P_VIDOSDxB_OSD_RBX_F(PANEL_WIDTH - 1 + s5pcfb_fimd.xoffset) |
- S5P_VIDOSDxB_OSD_RBY_F(PANEL_HEIGHT - 1 + s5pcfb_fimd.yoffset), S5P_VIDOSD0B);
-
- /* set framebuffer start address */
- writel(s5pcfb_fimd.screen, S5P_VIDW00ADD0B0);
-
- /* set framebuffer end address */
- writel((readl(S5P_VIDW00ADD0B0) + (page_width + offset) * s5pcfb_fimd.yres),
- S5P_VIDW00ADD1B0);
-
- /* set framebuffer size */
- fb_size = S5P_VIDWxxADD2_OFFSIZE_F(offset) |
- (S5P_VIDWxxADD2_PAGEWIDTH_F(page_width));
-
- writel(fb_size, S5P_VIDW00ADD2);
-
- udebug("fb_size at s5pc_lcd_init=%d, page_width=%d\n", fb_size, page_width);
-
- /* set window0 conguration register */
- s5pcfb_fimd.wincon0 = S5P_WINCONx_WSWP_ENABLE |
- S5P_WINCONx_BURSTLEN_16WORD |
- S5P_WINCONx_BPPMODE_F_24BPP_888;
-
- s5pcfb_fimd.bpp = S5P_LCD_BPP;
- s5pcfb_fimd.bytes_per_pixel = s5pcfb_fimd.bpp / 8;
-
- /* set registers */
- writel(s5pcfb_fimd.wincon0, S5P_WINCON0);
- writel(s5pcfb_fimd.vidcon0, S5P_VIDCON0);
- writel(s5pcfb_fimd.vidcon1, S5P_VIDCON1);
- writel(s5pcfb_fimd.vidtcon0, S5P_VIDTCON0);
- writel(s5pcfb_fimd.vidtcon1, S5P_VIDTCON1);
- writel(s5pcfb_fimd.vidtcon2, S5P_VIDTCON2);
- writel(s5pcfb_fimd.vidintcon0, S5P_VIDINTCON0);
- writel(s5pcfb_fimd.vidintcon1, S5P_VIDINTCON1);
-
- writel(s5pcfb_fimd.vidosd0a, S5P_VIDOSD0A);
- writel(s5pcfb_fimd.vidosd0b, S5P_VIDOSD0B);
- writel(s5pcfb_fimd.vidosd0c, S5P_VIDOSD0C);
- writel(s5pcfb_fimd.wpalcon, S5P_WPALCON);
-
- /* enable window0 */
- writel((readl(S5P_WINCON0) | S5P_WINCONx_ENWIN_F_ENABLE), S5P_WINCON0);
- writel((readl(S5P_VIDCON0) | S5P_VIDCON0_ENVID_ENABLE | S5P_VIDCON0_ENVID_F_ENABLE),
- S5P_VIDCON0);
-}
-
-ulong s5pc_fimd_calc_fbsize(void)
-{
- return (s5pcfb_fimd.xres * s5pcfb_fimd.yres * s5pcfb_fimd.bytes_per_pixel);
-}
/*
- * LCD panel support for the Samsung TickerTape board
+ * LCD panel driver for Board based on S5PC100 and S5PC110.
*
* Author: InKi Dae <inki.dae@samsung.com>
*
#include <linux/types.h>
#include <asm/io.h>
+#include <asm/arch/cpu.h>
#define SLEEPMSEC 0x1000
#define ENDDEF 0x2000
#define DEFMASK 0xFF00
-#define COMMAND_ONLY 0xFE
+#define COMMAND_ONLY 0xFE
#define DATA_ONLY 0xFF
-#define S5PCFB_CS_LOW __raw_writel(__raw_readl(0xE0300304) & 0xdf, 0xE0300304)
-#define S5PCFB_CS_HIGH __raw_writel(__raw_readl(0xE0300304) | 0x20, 0xE0300304)
-#define S5PCFB_CLK_LOW __raw_writel(__raw_readl(0xE0300304) & 0xbf, 0xE0300304)
-#define S5PCFB_CLK_HIGH __raw_writel(__raw_readl(0xE0300304) | 0x40, 0xE0300304)
-#define S5PCFB_SDA_LOW __raw_writel(__raw_readl(0xE0300304) & 0x7f, 0xE0300304)
-#define S5PCFB_SDA_HIGH __raw_writel(__raw_readl(0xE0300304) | 0x80, 0xE0300304)
+#define S5PCFB_C100_CS_LOW __raw_writel(__raw_readl(0xE0300304) & 0xdf, 0xE0300304)
+#define S5PCFB_C100_CS_HIGH __raw_writel(__raw_readl(0xE0300304) | 0x20, 0xE0300304)
+#define S5PCFB_C100_CLK_LOW __raw_writel(__raw_readl(0xE0300304) & 0xbf, 0xE0300304)
+#define S5PCFB_C100_CLK_HIGH __raw_writel(__raw_readl(0xE0300304) | 0x40, 0xE0300304)
+#define S5PCFB_C100_SDA_LOW __raw_writel(__raw_readl(0xE0300304) & 0x7f, 0xE0300304)
+#define S5PCFB_C100_SDA_HIGH __raw_writel(__raw_readl(0xE0300304) | 0x80, 0xE0300304)
+
+#define S5PCFB_C110_CS_LOW writel(readl(0xE02002E4) & 0xfd, 0xE02002E4)
+#define S5PCFB_C110_CS_HIGH writel(readl(0xE02002E4) | 0x02, 0xE02002E4)
+#define S5PCFB_C110_CLK_LOW writel(readl(0xE0200344) & 0xfd, 0xE0200344)
+#define S5PCFB_C110_CLK_HIGH writel(readl(0xE0200344) | 0x02, 0xE0200344)
+#define S5PCFB_C110_SDA_LOW writel(readl(0xE0200344) & 0xf7, 0xE0200344)
+#define S5PCFB_C110_SDA_HIGH writel(readl(0xE0200344) | 0x08, 0xE0200344)
const unsigned short SEQ_DISPLAY_ON[] = {
0x14, 0x03,
ENDDEF, 0x0000
};
-static void tl2796_spi_write_byte(unsigned char address, unsigned char command)
+static void tl2796_c100_spi_write_byte(unsigned char address, unsigned char command)
+{
+ int j;
+ unsigned char DELAY=1;
+ unsigned short data;
+
+ data = (address << 8) + command;
+
+ S5PCFB_C100_CS_HIGH;
+ S5PCFB_C100_SDA_HIGH;
+ S5PCFB_C100_CLK_HIGH;
+ udelay(DELAY);
+
+ S5PCFB_C100_CS_LOW;
+ udelay(DELAY);
+
+ for (j = 15; j >= 0; j--)
+ {
+ S5PCFB_C100_CLK_LOW;
+
+ /* data high or low */
+ if ((data >> j) & 0x0001)
+ S5PCFB_C100_SDA_HIGH;
+ else
+ S5PCFB_C100_SDA_LOW;
+
+ udelay(DELAY);
+
+ S5PCFB_C100_CLK_HIGH;
+ udelay(DELAY);
+ }
+
+ S5PCFB_C100_CS_HIGH;
+ udelay(DELAY);
+}
+
+static void tl2796_c110_spi_write_byte(unsigned char address, unsigned char command)
{
- int j;
+ int j;
unsigned char DELAY=1;
unsigned short data;
data = (address << 8) + command;
- S5PCFB_CS_HIGH;
- S5PCFB_SDA_HIGH;
- S5PCFB_CLK_HIGH;
+ S5PCFB_C110_CS_HIGH;
+ S5PCFB_C110_SDA_HIGH;
+ S5PCFB_C110_CLK_HIGH;
udelay(DELAY);
- S5PCFB_CS_LOW;
+ S5PCFB_C110_CS_LOW;
udelay(DELAY);
for (j = 15; j >= 0; j--)
{
- S5PCFB_CLK_LOW;
+ S5PCFB_C110_CLK_LOW;
/* data high or low */
if ((data >> j) & 0x0001)
- S5PCFB_SDA_HIGH;
+ S5PCFB_C110_SDA_HIGH;
else
- S5PCFB_SDA_LOW;
+ S5PCFB_C110_SDA_LOW;
udelay(DELAY);
- S5PCFB_CLK_HIGH;
+ S5PCFB_C110_CLK_HIGH;
udelay(DELAY);
}
- S5PCFB_CS_HIGH;
+ S5PCFB_C110_CS_HIGH;
udelay(DELAY);
}
static void tl2796_spi_write(unsigned char address, unsigned char command)
{
- if(address != DATA_ONLY)
- tl2796_spi_write_byte(0x70, address);
+ if (cpu_is_s5pc110()) {
+ if(address != DATA_ONLY)
+ tl2796_c110_spi_write_byte(0x70, address);
+
+ tl2796_c110_spi_write_byte(0x72, command);
+ } else {
+ if(address != DATA_ONLY)
+ tl2796_c100_spi_write_byte(0x70, address);
- tl2796_spi_write_byte(0x72, command);
+ tl2796_c100_spi_write_byte(0x72, command);
+ }
}
static void tl2796_panel_send_sequence(const unsigned short *wbuf)
}
}
-void tl2796_panel_power_on(void)
+void tl2796_c100_panel_power_on(void)
{
/* set gpio data for MLCD_RST to HIGH */
- __raw_writel(__raw_readl(0xE0300C24) | 0x80, 0xE0300C24);
+ writel(readl(0xE0300C24) | 0x80, 0xE0300C24);
/* set gpio data for MLCD_ON to HIGH */
- __raw_writel(__raw_readl(0xE0300224) | 0x8, 0xE0300224);
+ writel(readl(0xE0300224) | 0x8, 0xE0300224);
udelay(25000);
/* set gpio data for MLCD_RST to LOW */
- __raw_writel(__raw_readl(0xE0300C24) & 0x7f, 0xE0300C24);
+ writel(readl(0xE0300C24) & 0x7f, 0xE0300C24);
udelay(20);
/* set gpio data for MLCD_RST to HIGH */
- __raw_writel(__raw_readl(0xE0300C24) | 0x80, 0xE0300C24);
+ writel(readl(0xE0300C24) | 0x80, 0xE0300C24);
udelay(20000);
tl2796_panel_send_sequence(SEQ_STANDBY_OFF);
}
-static inline void tl2796_panel_hw_reset(void)
+void tl2796_c110_panel_power_on(void)
+{
+ /* set gpio data for MLCD_RST to HIGH */
+ writel(readl(0xE0200C24) | 0x80, 0xE0200C24);
+ /* set gpio data for MLCD_ON to HIGH */
+ writel(readl(0xE0200264) | 0x8, 0xE0200264);
+ udelay(25000);
+
+ /* set gpio data for MLCD_RST to LOW */
+ writel(readl(0xE0200C24) & 0x7f, 0xE0200C24);
+ udelay(20);
+ /* set gpio data for MLCD_RST to HIGH */
+ writel(readl(0xE0200C24) | 0x80, 0xE0200C24);
+
+ udelay(20000);
+
+ tl2796_panel_send_sequence(SEQ_SETTING);
+ tl2796_panel_send_sequence(SEQ_STANDBY_OFF);
+}
+
+static inline void tl2796_c100_panel_hw_reset(void)
+{
+ /* set gpio pin for MLCD_RST to LOW */
+ writel(readl(0xE0300C24) & 0x7f, 0xE0300C24);
+ udelay(1); /* Shorter than 5 usec */
+ /* set gpio pin for MLCD_RST to HIGH */
+ writel(readl(0xE0300C24) | 0x80, 0xE0300C24);
+ udelay(10000);
+}
+
+static inline void tl2796_c110_panel_hw_reset(void)
{
/* set gpio pin for MLCD_RST to LOW */
- __raw_writel(__raw_readl(0xE0300C24) & 0x7f, 0xE0300C24);
+ writel(readl(0xE0200C24) & 0x7f, 0xE0200C24);
udelay(1); /* Shorter than 5 usec */
/* set gpio pin for MLCD_RST to HIGH */
- __raw_writel(__raw_readl(0xE0300C24) | 0x80, 0xE0300C24);
+ writel(readl(0xE0200C24) | 0x80, 0xE0200C24);
udelay(10000);
}
tl2796_panel_send_sequence(SEQ_DISPLAY_OFF);
}
-void tl2796_panel_init(void)
+void tl2796_c100_panel_init(void)
+{
+ /* set gpio pin for DISPLAY_CS to HIGH */
+ writel(readl(0xE0300304) | 0x20, 0xE0300304);
+ /* set gpio pin for DISPLAY_CLK to HIGH */
+ writel(readl(0xE0300304) | 0x40, 0xE0300304);
+ /* set gpio pin for DISPLAY_SI to HIGH */
+ writel(readl(0xE0300304) | 0x80, 0xE0300304);
+}
+
+void tl2796_c110_panel_init(void)
{
/* set gpio pin for DISPLAY_CS to HIGH */
- __raw_writel(__raw_readl(0xE0300304) | 0x20, 0xE0300304);
+ writel(readl(0xE02002E4) | 0x02, 0xE02002E4);
/* set gpio pin for DISPLAY_CLK to HIGH */
- __raw_writel(__raw_readl(0xE0300304) | 0x40, 0xE0300304);
+ writel(readl(0xE0200344) | 0x02, 0xE0200344);
/* set gpio pin for DISPLAY_SI to HIGH */
- __raw_writel(__raw_readl(0xE0300304) | 0x80, 0xE0300304);
+ writel(readl(0xE0200344) | 0x08, 0xE0200344);
}
--- /dev/null
+/* linux/asm/arch/regs-fb.h
+ *
+ * Register definition file for Samsung Display Controller (FIMD) driver
+ *
+ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics
+ * http://www.samsungsemi.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _REGS_FB_H
+#define _REGS_FB_H
+
+#define S5P_LCDREG(x) (x)
+#define S5P_WINCON(x) S5P_LCDREG(0x0020 + (x * 0x04))
+#define S5P_VIDOSD_A(x) S5P_LCDREG(0x0040 + (x * 0x10))
+#define S5P_VIDOSD_B(x) S5P_LCDREG(0x0044 + (x * 0x10))
+#define S5P_VIDOSD_C(x) S5P_LCDREG(0x0048 + (x * 0x10))
+#define S5P_VIDOSD_D(x) S5P_LCDREG(0x004C + (x * 0x10))
+#define S5P_VIDADDR_START0(x) S5P_LCDREG(0x00A0 + (x * 0x08))
+#define S5P_VIDADDR_START1(x) S5P_LCDREG(0x00A4 + (x * 0x08))
+#define S5P_VIDADDR_END0(x) S5P_LCDREG(0x00D0 + (x * 0x08))
+#define S5P_VIDADDR_END1(x) S5P_LCDREG(0x00D4 + (x * 0x08))
+#define S5P_VIDADDR_SIZE(x) S5P_LCDREG(0x0100 + (x * 0x04))
+#define S5P_KEYCON(x) S5P_LCDREG(0x0140 + ((x - 1) * 0x08))
+#define S5P_KEYVAL(x) S5P_LCDREG(0x0144 + ((x - 1) * 0x08))
+
+/*
+ * Register Map
+*/
+#define S5P_VIDCON0 S5P_LCDREG(0x0000) /* Video control 0 */
+#define S5P_VIDCON1 S5P_LCDREG(0x0004) /* Video control 1 */
+#define S5P_VIDCON2 S5P_LCDREG(0x0008) /* Video control 2 */
+#define S5P_PRTCON S5P_LCDREG(0x000C) /* Protect control */
+
+#define S5P_VIDTCON0 S5P_LCDREG(0x0010) /* Video time control 0 */
+#define S5P_VIDTCON1 S5P_LCDREG(0x0014) /* Video time control 1 */
+#define S5P_VIDTCON2 S5P_LCDREG(0x0018) /* Video time control 2 */
+
+#define S5P_WINCON0 S5P_LCDREG(0x0020) /* Window control 0 */
+#define S5P_WINCON1 S5P_LCDREG(0x0024) /* Window control 1 */
+#define S5P_WINCON2 S5P_LCDREG(0x0028) /* Window control 2 */
+#define S5P_WINCON3 S5P_LCDREG(0x002C) /* Window control 3 */
+#define S5P_WINCON4 S5P_LCDREG(0x0030) /* Window control 4 */
+
+#define S5P_VIDOSD0A S5P_LCDREG(0x0040) /* Video Window 0 position control */
+#define S5P_VIDOSD0B S5P_LCDREG(0x0044) /* Video Window 0 position control1 */
+#define S5P_VIDOSD0C S5P_LCDREG(0x0048) /* Video Window 0 position control */
+
+#define S5P_VIDOSD1A S5P_LCDREG(0x0050) /* Video Window 1 position control */
+#define S5P_VIDOSD1B S5P_LCDREG(0x0054) /* Video Window 1 position control */
+#define S5P_VIDOSD1C S5P_LCDREG(0x0058) /* Video Window 1 position control */
+#define S5P_VIDOSD1D S5P_LCDREG(0x005C) /* Video Window 1 position control */
+
+#define S5P_VIDOSD2A S5P_LCDREG(0x0060) /* Video Window 2 position control */
+#define S5P_VIDOSD2B S5P_LCDREG(0x0064) /* Video Window 2 position control */
+#define S5P_VIDOSD2C S5P_LCDREG(0x0068) /* Video Window 2 position control */
+#define S5P_VIDOSD2D S5P_LCDREG(0x006C) /* Video Window 2 position control */
+
+#define S5P_VIDOSD3A S5P_LCDREG(0x0070) /* Video Window 3 position control */
+#define S5P_VIDOSD3B S5P_LCDREG(0x0074) /* Video Window 3 position control */
+#define S5P_VIDOSD3C S5P_LCDREG(0x0078) /* Video Window 3 position control */
+
+#define S5P_VIDOSD4A S5P_LCDREG(0x0080) /* Video Window 4 position control */
+#define S5P_VIDOSD4B S5P_LCDREG(0x0084) /* Video Window 4 position control */
+#define S5P_VIDOSD4C S5P_LCDREG(0x0088) /* Video Window 4 position control */
+
+#define S5P_VIDW00ADD0B0 S5P_LCDREG(0x00A0) /* Window 0 buffer start address, buffer 0 */
+#define S5P_VIDW00ADD0B1 S5P_LCDREG(0x00A4) /* Window 0 buffer start address, buffer 1 */
+#define S5P_VIDW01ADD0B0 S5P_LCDREG(0x00A8) /* Window 1 buffer start address, buffer 0 */
+#define S5P_VIDW01ADD0B1 S5P_LCDREG(0x00AC) /* Window 1 buffer start address, buffer 1 */
+#define S5P_VIDW02ADD0 S5P_LCDREG(0x00B0) /* Window 2 buffer start address, buffer 0 */
+#define S5P_VIDW03ADD0 S5P_LCDREG(0x00B8) /* Window 3 buffer start address, buffer 0 */
+#define S5P_VIDW04ADD0 S5P_LCDREG(0x00C0) /* Window 4 buffer start address, buffer 0 */
+#define S5P_VIDW00ADD1B0 S5P_LCDREG(0x00D0) /* Window 0 buffer end address, buffer 0 */
+#define S5P_VIDW00ADD1B1 S5P_LCDREG(0x00D4) /* Window 0 buffer end address, buffer 1 */
+#define S5P_VIDW01ADD1B0 S5P_LCDREG(0x00D8) /* Window 1 buffer end address, buffer 0 */
+#define S5P_VIDW01ADD1B1 S5P_LCDREG(0x00DC) /* Window 1 buffer end address, buffer 1 */
+#define S5P_VIDW02ADD1 S5P_LCDREG(0x00E0) /* Window 2 buffer end address */
+#define S5P_VIDW03ADD1 S5P_LCDREG(0x00E8) /* Window 3 buffer end address */
+#define S5P_VIDW04ADD1 S5P_LCDREG(0x00F0) /* Window 4 buffer end address */
+#define S5P_VIDW00ADD2 S5P_LCDREG(0x0100) /* Window 0 buffer size */
+#define S5P_VIDW01ADD2 S5P_LCDREG(0x0104) /* Window 1 buffer size */
+#define S5P_VIDW02ADD2 S5P_LCDREG(0x0108) /* Window 2 buffer size */
+#define S5P_VIDW03ADD2 S5P_LCDREG(0x010C) /* Window 3 buffer size */
+#define S5P_VIDW04ADD2 S5P_LCDREG(0x0110) /* Window 4 buffer size */
+
+#define S5P_VP1TCON0 S5P_LCDREG(0x0118) /* VP1 interface timing control 0 */
+#define S5P_VP1TCON1 S5P_LCDREG(0x011C) /* VP1 interface timing control 1 */
+
+#define S5P_VIDINTCON0 S5P_LCDREG(0x0130) /* Indicate the Video interrupt control */
+#define S5P_VIDINTCON1 S5P_LCDREG(0x0134) /* Video Interrupt Pending */
+
+#define S5P_W1KEYCON0 S5P_LCDREG(0x0140) /* Color key control */
+#define S5P_W1KEYCON1 S5P_LCDREG(0x0144) /* Color key value (transparent value) */
+#define S5P_W2KEYCON0 S5P_LCDREG(0x0148) /* Color key control */
+#define S5P_W2KEYCON1 S5P_LCDREG(0x014C) /* Color key value (transparent value) */
+#define S5P_W3KEYCON0 S5P_LCDREG(0x0150) /* Color key control */
+#define S5P_W3KEYCON1 S5P_LCDREG(0x0154) /* Color key value (transparent value) */
+#define S5P_W4KEYCON0 S5P_LCDREG(0x0158) /* Color key control */
+#define S5P_W4KEYCON1 S5P_LCDREG(0x015C) /* Color key value (transparent value) */
+
+#define S5P_W1KEYALPHA S5P_LCDREG(0x0160) /* Color key alpha value */
+#define S5P_W2KEYALPHA S5P_LCDREG(0x0164) /* Color key alpha value */
+#define S5P_W3KEYALPHA S5P_LCDREG(0x0168) /* Color key alpha value */
+#define S5P_W4KEYALPHA S5P_LCDREG(0x016C) /* Color key alpha value */
+
+#define S5P_DITHMODE S5P_LCDREG(0x0170) /* Dithering mode */
+
+#define S5P_WIN0MAP S5P_LCDREG(0x0180) /* Window color control */
+#define S5P_WIN1MAP S5P_LCDREG(0x0184) /* Window color control */
+#define S5P_WIN2MAP S5P_LCDREG(0x0188) /* Window color control */
+#define S5P_WIN3MAP S5P_LCDREG(0x018C) /* Window color control */
+#define S5P_WIN4MAP S5P_LCDREG(0x0190) /* Window color control */
+
+#define S5P_WPALCON_H S5P_LCDREG(0x019C) /* Window Palette control */
+#define S5P_WPALCON_L S5P_LCDREG(0x01A0) /* Window Palette control */
+
+#define S5P_VIDW0ALPHA0 S5P_LCDREG(0x0200) /* Window 0 alpha value 0 */
+#define S5P_VIDW0ALPHA1 S5P_LCDREG(0x0204) /* Window 0 alpha value 1 */
+#define S5P_VIDW1ALPHA0 S5P_LCDREG(0x0208) /* Window 1 alpha value 0 */
+#define S5P_VIDW1ALPHA1 S5P_LCDREG(0x020C) /* Window 1 alpha value 1 */
+#define S5P_VIDW2ALPHA0 S5P_LCDREG(0x0210) /* Window 2 alpha value 0 */
+#define S5P_VIDW2ALPHA1 S5P_LCDREG(0x0214) /* Window 2 alpha value 1 */
+#define S5P_VIDW3ALPHA0 S5P_LCDREG(0x0218) /* Window 3 alpha value 0 */
+#define S5P_VIDW3ALPHA1 S5P_LCDREG(0x021C) /* Window 3 alpha value 1 */
+#define S5P_VIDW4ALPHA0 S5P_LCDREG(0x0220) /* Window 4 alpha value 0 */
+#define S5P_VIDW4ALPHA1 S5P_LCDREG(0x0224) /* Window 4 alpha value 1 */
+
+#define S5P_BLENDEQ1 S5P_LCDREG(0x0244) /* Window 1 blending equation control */
+#define S5P_BLENDEQ2 S5P_LCDREG(0x0248) /* Window 2 blending equation control */
+#define S5P_BLENDEQ3 S5P_LCDREG(0x024C) /* Window 3 blending equation control */
+#define S5P_BLENDEQ4 S5P_LCDREG(0x0250) /* Window 4 blending equation control */
+#define S5P_BLENDCON S5P_LCDREG(0x0260) /* Blending control */
+
+/*
+ * Bit Definitions
+*/
+
+/* VIDCON0 */
+#define S5P_VIDCON0_DSI_DISABLE (0 << 30)
+#define S5P_VIDCON0_DSI_ENABLE (1 << 30)
+#define S5P_VIDCON0_SCAN_PROGRESSIVE (0 << 29)
+#define S5P_VIDCON0_SCAN_INTERLACE (1 << 29)
+#define S5P_VIDCON0_SCAN_MASK (1 << 29)
+#define S5P_VIDCON0_VIDOUT_RGB (0 << 26)
+#define S5P_VIDCON0_VIDOUT_ITU (1 << 26)
+#define S5P_VIDCON0_VIDOUT_I80LDI0 (2 << 26)
+#define S5P_VIDCON0_VIDOUT_I80LDI1 (3 << 26)
+#define S5P_VIDCON0_VIDOUT_MASK (3 << 26)
+#define S5P_VIDCON0_PNRMODE_RGB_P (0 << 17)
+#define S5P_VIDCON0_PNRMODE_BGR_P (1 << 17)
+#define S5P_VIDCON0_PNRMODE_RGB_S (2 << 17)
+#define S5P_VIDCON0_PNRMODE_BGR_S (3 << 17)
+#define S5P_VIDCON0_PNRMODE_MASK (3 << 17)
+#define S5P_VIDCON0_PNRMODE_SHIFT (17)
+#define S5P_VIDCON0_CLKVALUP_ALWAYS (0 << 16)
+#define S5P_VIDCON0_CLKVALUP_START_FRAME (1 << 16)
+#define S5P_VIDCON0_CLKVALUP_MASK (1 << 16)
+#define S5P_VIDCON0_CLKVAL_F(x) (((x) & 0xff) << 6)
+#define S5P_VIDCON0_VCLKEN_NORMAL (0 << 5)
+#define S5P_VIDCON0_VCLKEN_FREERUN (1 << 5)
+#define S5P_VIDCON0_VCLKEN_MASK (1 << 5)
+#define S5P_VIDCON0_CLKDIR_DIRECTED (0 << 4)
+#define S5P_VIDCON0_CLKDIR_DIVIDED (1 << 4)
+#define S5P_VIDCON0_CLKDIR_MASK (1 << 4)
+#define S5P_VIDCON0_CLKSEL_HCLK (0 << 2)
+#define S5P_VIDCON0_CLKSEL_SCLK (1 << 2)
+#define S5P_VIDCON0_CLKSEL_MASK (1 << 2)
+#define S5P_VIDCON0_ENVID_ENABLE (1 << 1)
+#define S5P_VIDCON0_ENVID_DISABLE (0 << 1)
+#define S5P_VIDCON0_ENVID_F_ENABLE (1 << 0)
+#define S5P_VIDCON0_ENVID_F_DISABLE (0 << 0)
+
+/* VIDCON1 */
+#define S5P_VIDCON1_IVCLK_FALLING_EDGE (0 << 7)
+#define S5P_VIDCON1_IVCLK_RISING_EDGE (1 << 7)
+#define S5P_VIDCON1_IHSYNC_NORMAL (0 << 6)
+#define S5P_VIDCON1_IHSYNC_INVERT (1 << 6)
+#define S5P_VIDCON1_IVSYNC_NORMAL (0 << 5)
+#define S5P_VIDCON1_IVSYNC_INVERT (1 << 5)
+#define S5P_VIDCON1_IVDEN_NORMAL (0 << 4)
+#define S5P_VIDCON1_IVDEN_INVERT (1 << 4)
+
+/* VIDCON2 */
+#define S5P_VIDCON2_EN601_DISABLE (0 << 23)
+#define S5P_VIDCON2_EN601_ENABLE (1 << 23)
+#define S5P_VIDCON2_EN601_MASK (1 << 23)
+#define S5P_VIDCON2_ORGYUV_YCBCR (0 << 8)
+#define S5P_VIDCON2_ORGYUV_CBCRY (1 << 8)
+#define S5P_VIDCON2_ORGYUV_MASK (1 << 8)
+#define S5P_VIDCON2_YUVORD_CBCR (0 << 7)
+#define S5P_VIDCON2_YUVORD_CRCB (1 << 7)
+#define S5P_VIDCON2_YUVORD_MASK (1 << 7)
+
+/* PRTCON */
+#define S5P_PRTCON_UPDATABLE (0 << 11)
+#define S5P_PRTCON_PROTECT (1 << 11)
+
+/* VIDTCON0 */
+#define S5P_VIDTCON0_VBPDE(x) (((x) & 0xff) << 24)
+#define S5P_VIDTCON0_VBPD(x) (((x) & 0xff) << 16)
+#define S5P_VIDTCON0_VFPD(x) (((x) & 0xff) << 8)
+#define S5P_VIDTCON0_VSPW(x) (((x) & 0xff) << 0)
+
+/* VIDTCON1 */
+#define S5P_VIDTCON1_VFPDE(x) (((x) & 0xff) << 24)
+#define S5P_VIDTCON1_HBPD(x) (((x) & 0xff) << 16)
+#define S5P_VIDTCON1_HFPD(x) (((x) & 0xff) << 8)
+#define S5P_VIDTCON1_HSPW(x) (((x) & 0xff) << 0)
+
+/* VIDTCON2 */
+#define S5P_VIDTCON2_LINEVAL(x) (((x) & 0x7ff) << 11)
+#define S5P_VIDTCON2_HOZVAL(x) (((x) & 0x7ff) << 0)
+
+/* Window 0~4 Control - WINCONx */
+#define S5P_WINCON_DATAPATH_DMA (0 << 22)
+#define S5P_WINCON_DATAPATH_LOCAL (1 << 22)
+#define S5P_WINCON_DATAPATH_MASK (1 << 22)
+#define S5P_WINCON_BUFSEL_0 (0 << 20)
+#define S5P_WINCON_BUFSEL_1 (1 << 20)
+#define S5P_WINCON_BUFSEL_MASK (1 << 20)
+#define S5P_WINCON_BUFSEL_SHIFT (20)
+#define S5P_WINCON_BUFAUTO_DISABLE (0 << 19)
+#define S5P_WINCON_BUFAUTO_ENABLE (1 << 19)
+#define S5P_WINCON_BUFAUTO_MASK (1 << 19)
+#define S5P_WINCON_BITSWP_DISABLE (0 << 18)
+#define S5P_WINCON_BITSWP_ENABLE (1 << 18)
+#define S5P_WINCON_BITSWP_SHIFT (18)
+#define S5P_WINCON_BYTESWP_DISABLE (0 << 17)
+#define S5P_WINCON_BYTESWP_ENABLE (1 << 17)
+#define S5P_WINCON_BYTESWP_SHIFT (17)
+#define S5P_WINCON_HAWSWP_DISABLE (0 << 16)
+#define S5P_WINCON_HAWSWP_ENABLE (1 << 16)
+#define S5P_WINCON_HAWSWP_SHIFT (16)
+#define S5P_WINCON_WSWP_DISABLE (0 << 15)
+#define S5P_WINCON_WSWP_ENABLE (1 << 15)
+#define S5P_WINCON_WSWP_SHIFT (15)
+#define S5P_WINCON_INRGB_RGB (0 << 13)
+#define S5P_WINCON_INRGB_YUV (1 << 13)
+#define S5P_WINCON_INRGB_MASK (1 << 13)
+#define S5P_WINCON_BURSTLEN_16WORD (0 << 9)
+#define S5P_WINCON_BURSTLEN_8WORD (1 << 9)
+#define S5P_WINCON_BURSTLEN_4WORD (2 << 9)
+#define S5P_WINCON_BURSTLEN_MASK (3 << 9)
+#define S5P_WINCON_ALPHA_MULTI_DISABLE (0 << 7)
+#define S5P_WINCON_ALPHA_MULTI_ENABLE (1 << 7)
+#define S5P_WINCON_BLD_PLANE (0 << 6)
+#define S5P_WINCON_BLD_PIXEL (1 << 6)
+#define S5P_WINCON_BLD_MASK (1 << 6)
+#define S5P_WINCON_BPPMODE_1BPP (0 << 2)
+#define S5P_WINCON_BPPMODE_2BPP (1 << 2)
+#define S5P_WINCON_BPPMODE_4BPP (2 << 2)
+#define S5P_WINCON_BPPMODE_8BPP_PAL (3 << 2)
+#define S5P_WINCON_BPPMODE_8BPP (4 << 2)
+#define S5P_WINCON_BPPMODE_16BPP_565 (5 << 2)
+#define S5P_WINCON_BPPMODE_16BPP_A555 (6 << 2)
+#define S5P_WINCON_BPPMODE_18BPP_666 (8 << 2)
+#define S5P_WINCON_BPPMODE_18BPP_A665 (9 << 2)
+#define S5P_WINCON_BPPMODE_24BPP_888 (0xb << 2)
+#define S5P_WINCON_BPPMODE_24BPP_A887 (0xc << 2)
+#define S5P_WINCON_BPPMODE_32BPP (0xd << 2)
+#define S5P_WINCON_BPPMODE_16BPP_A444 (0xe << 2)
+#define S5P_WINCON_BPPMODE_15BPP_555 (0xf << 2)
+#define S5P_WINCON_BPPMODE_MASK (0xf << 2)
+#define S5P_WINCON_BPPMODE_SHIFT (2)
+#define S5P_WINCON_ALPHA0_SEL (0 << 1)
+#define S5P_WINCON_ALPHA1_SEL (1 << 1)
+#define S5P_WINCON_ALPHA_SEL_MASK (1 << 1)
+#define S5P_WINCON_ENWIN_DISABLE (0 << 0)
+#define S5P_WINCON_ENWIN_ENABLE (1 << 0)
+
+/* WINCON1 special */
+#define S5P_WINCON1_VP_DISABLE (0 << 24)
+#define S5P_WINCON1_VP_ENABLE (1 << 24)
+#define S5P_WINCON1_LOCALSEL_FIMC1 (0 << 23)
+#define S5P_WINCON1_LOCALSEL_VP (1 << 23)
+#define S5P_WINCON1_LOCALSEL_MASK (1 << 23)
+
+/* VIDOSDxA, VIDOSDxB */
+#define S5P_VIDOSD_LEFT_X(x) (((x) & 0x7ff) << 11)
+#define S5P_VIDOSD_TOP_Y(x) (((x) & 0x7ff) << 0)
+#define S5P_VIDOSD_RIGHT_X(x) (((x) & 0x7ff) << 11)
+#define S5P_VIDOSD_BOTTOM_Y(x) (((x) & 0x7ff) << 0)
+
+/* VIDOSD0C, VIDOSDxD */
+#define S5P_VIDOSD_SIZE(x) (((x) & 0xffffff) << 0)
+
+/* VIDOSDxC (1~4) */
+#define S5P_VIDOSD_ALPHA0_R(x) (((x) & 0xf) << 20)
+#define S5P_VIDOSD_ALPHA0_G(x) (((x) & 0xf) << 16)
+#define S5P_VIDOSD_ALPHA0_B(x) (((x) & 0xf) << 12)
+#define S5P_VIDOSD_ALPHA1_R(x) (((x) & 0xf) << 8)
+#define S5P_VIDOSD_ALPHA1_G(x) (((x) & 0xf) << 4)
+#define S5P_VIDOSD_ALPHA1_B(x) (((x) & 0xf) << 0)
+#define S5P_VIDOSD_ALPHA0_SHIFT (12)
+#define S5P_VIDOSD_ALPHA1_SHIFT (0)
+
+/* Start Address */
+#define S5P_VIDADDR_START_VBANK(x) (((x) & 0xff) << 24)
+#define S5P_VIDADDR_START_VBASEU(x) (((x) & 0xffffff) << 0)
+
+/* End Address */
+#define S5P_VIDADDR_END_VBASEL(x) (((x) & 0xffffff) << 0)
+
+/* Buffer Size */
+#define S5P_VIDADDR_OFFSIZE(x) (((x) & 0x1fff) << 13)
+#define S5P_VIDADDR_PAGEWIDTH(x) (((x) & 0x1fff) << 0)
+
+/* VIDINTCON0 */
+#define S5P_VIDINTCON0_SYSMAINCON_DISABLE (0 << 19)
+#define S5P_VIDINTCON0_SYSMAINCON_ENABLE (1 << 19)
+#define S5P_VIDINTCON0_SYSSUBCON_DISABLE (0 << 18)
+#define S5P_VIDINTCON0_SYSSUBCON_ENABLE (1 << 18)
+#define S5P_VIDINTCON0_SYSIFDONE_DISABLE (0 << 17)
+#define S5P_VIDINTCON0_SYSIFDONE_ENABLE (1 << 17)
+#define S5P_VIDINTCON0_FRAMESEL0_BACK (0 << 15)
+#define S5P_VIDINTCON0_FRAMESEL0_VSYNC (1 << 15)
+#define S5P_VIDINTCON0_FRAMESEL0_ACTIVE (2 << 15)
+#define S5P_VIDINTCON0_FRAMESEL0_FRONT (3 << 15)
+#define S5P_VIDINTCON0_FRAMESEL0_MASK (3 << 15)
+#define S5P_VIDINTCON0_FRAMESEL1_NONE (0 << 13)
+#define S5P_VIDINTCON0_FRAMESEL1_BACK (1 << 13)
+#define S5P_VIDINTCON0_FRAMESEL1_VSYNC (2 << 13)
+#define S5P_VIDINTCON0_FRAMESEL1_FRONT (3 << 13)
+#define S5P_VIDINTCON0_INTFRMEN_DISABLE (0 << 12)
+#define S5P_VIDINTCON0_INTFRMEN_ENABLE (1 << 12)
+#define S5P_VIDINTCON0_FIFOSEL_WIN4 (1 << 11)
+#define S5P_VIDINTCON0_FIFOSEL_WIN3 (1 << 10)
+#define S5P_VIDINTCON0_FIFOSEL_WIN2 (1 << 9)
+#define S5P_VIDINTCON0_FIFOSEL_WIN1 (1 << 6)
+#define S5P_VIDINTCON0_FIFOSEL_WIN0 (1 << 5)
+#define S5P_VIDINTCON0_FIFOSEL_ALL (0x73 << 5)
+#define S5P_VIDINTCON0_FIFOSEL_MASK (0x73 << 5)
+#define S5P_VIDINTCON0_FIFOLEVEL_25 (0 << 2)
+#define S5P_VIDINTCON0_FIFOLEVEL_50 (1 << 2)
+#define S5P_VIDINTCON0_FIFOLEVEL_75 (2 << 2)
+#define S5P_VIDINTCON0_FIFOLEVEL_EMPTY (3 << 2)
+#define S5P_VIDINTCON0_FIFOLEVEL_FULL (4 << 2)
+#define S5P_VIDINTCON0_FIFOLEVEL_MASK (7 << 2)
+#define S5P_VIDINTCON0_INTFIFO_DISABLE (0 << 1)
+#define S5P_VIDINTCON0_INTFIFO_ENABLE (1 << 1)
+#define S5P_VIDINTCON0_INT_DISABLE (0 << 0)
+#define S5P_VIDINTCON0_INT_ENABLE (1 << 0)
+#define S5P_VIDINTCON0_INT_MASK (1 << 0)
+
+/* VIDINTCON1 */
+#define S5P_VIDINTCON1_INTVPPEND (1 << 5)
+#define S5P_VIDINTCON1_INTI80PEND (1 << 2)
+#define S5P_VIDINTCON1_INTFRMPEND (1 << 1)
+#define S5P_VIDINTCON1_INTFIFOPEND (1 << 0)
+
+/* WxKEYCON0 (1~4) */
+#define S5P_KEYCON0_KEYBLEN_DISABLE (0 << 26)
+#define S5P_KEYCON0_KEYBLEN_ENABLE (1 << 26)
+#define S5P_KEYCON0_KEY_DISABLE (0 << 25)
+#define S5P_KEYCON0_KEY_ENABLE (1 << 25)
+#define S5P_KEYCON0_DIRCON_MATCH_FG (0 << 24)
+#define S5P_KEYCON0_DIRCON_MATCH_BG (1 << 24)
+#define S5P_KEYCON0_COMPKEY(x) (((x) & 0xffffff) << 0)
+
+/* WxKEYCON1 (1~4) */
+#define S5P_KEYCON1_COLVAL(x) (((x) & 0xffffff) << 0)
+
+#endif /* _REGS_FB_H */
+++ /dev/null
-/* include/asm/arch/regs-lcd.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- * http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-
-#ifndef ___ASM_ARCH_REGS_LCD_H
-#define ___ASM_ARCH_REGS_LCD_H
-
-#define S5P_ADDR_BASE 0xE1F00000
-#define S5PCFB_ADDR(x) (S5P_ADDR_BASE + (x))
-#define S5P_LCD_BASE S5PCFB_ADDR(0xC100000)
-
-#define S5P_LCDREG(x) ((x) + S5P_LCD_BASE)
-
-/* LCD control registers */
-#define S5P_VIDCON0 S5P_LCDREG(0x00) /* Video control 0 register */
-#define S5P_VIDCON1 S5P_LCDREG(0x04) /* Video control 1 register */
-#define S5P_VIDCON2 S5P_LCDREG(0x08) /* Video control 2 register */
-#define S5P_VIDTCON0 S5P_LCDREG(0x10) /* Video time control 0 register */
-#define S5P_VIDTCON1 S5P_LCDREG(0x14) /* Video time control 1 register */
-#define S5P_VIDTCON2 S5P_LCDREG(0x18) /* Video time control 2 register */
-#define S5P_VIDTCON3 S5P_LCDREG(0x1C) /* Video time control 3 register */
-
-#define S5P_WINCON0 S5P_LCDREG(0x20) /* Window control 0 register */
-#define S5P_WINCON1 S5P_LCDREG(0x24) /* Window control 1 register */
-#define S5P_WINCON2 S5P_LCDREG(0x28) /* Window control 2 register */
-#define S5P_WINCON3 S5P_LCDREG(0x2C) /* Window control 3 register */
-#define S5P_WINCON4 S5P_LCDREG(0x30) /* Window control 4 register*/
-
-
-#define S5P_VIDOSD0A S5P_LCDREG(0x40) /* Video Window 0 position control register */
-#define S5P_VIDOSD0B S5P_LCDREG(0x44) /* Video Window 0 position control register1 */
-#define S5P_VIDOSD0C S5P_LCDREG(0x48) /* Video Window 0 position control register */
-
-#define S5P_VIDOSD1A S5P_LCDREG(0x50) /* Video Window 1 position control register */
-#define S5P_VIDOSD1B S5P_LCDREG(0x54) /* Video Window 1 position control register */
-#define S5P_VIDOSD1C S5P_LCDREG(0x58) /* Video Window 1 position control register */
-#define S5P_VIDOSD1D S5P_LCDREG(0x5C) /* Video Window 1 position control register */
-
-#define S5P_VIDOSD2A S5P_LCDREG(0x60) /* Video Window 2 position control register */
-#define S5P_VIDOSD2B S5P_LCDREG(0x64) /* Video Window 2 position control register */
-#define S5P_VIDOSD2C S5P_LCDREG(0x68) /* Video Window 2 position control register */
-#define S5P_VIDOSD2D S5P_LCDREG(0x6C) /* Video Window 2 position control register */
-
-#define S5P_VIDOSD3A S5P_LCDREG(0x70) /* Video Window 3 position control register */
-#define S5P_VIDOSD3B S5P_LCDREG(0x74) /* Video Window 3 position control register */
-#define S5P_VIDOSD3C S5P_LCDREG(0x78) /* Video Window 3 position control register */
-
-#define S5P_VIDOSD4A S5P_LCDREG(0x80) /* Video Window 4 position control register */
-#define S5P_VIDOSD4B S5P_LCDREG(0x84) /* Video Window 4 position control register */
-#define S5P_VIDOSD4C S5P_LCDREG(0x88) /* Video Window 4 position control register */
-
-#define S5P_VIDW00ADD2B0 S5P_LCDREG(0x94) /* LCD CONTROL 1 */
-#define S5P_VIDW00ADD2B1 S5P_LCDREG(0x98) /* LCD CONTROL 1 */
-
-#define S5P_VIDW00ADD0B0 S5P_LCDREG(0x0A0) /* Window 0 buffer start address register, buffer 0 */
-#define S5P_VIDW00ADD0B1 S5P_LCDREG(0x0A4) /* Window 0 buffer start address register, buffer 1 */
-#define S5P_VIDW01ADD0B0 S5P_LCDREG(0x0A8) /* Window 1 buffer start address register, buffer 0 */
-#define S5P_VIDW01ADD0B1 S5P_LCDREG(0x0AC) /* Window 1 buffer start address register, buffer 1 */
-#define S5P_VIDW02ADD0 S5P_LCDREG(0x0B0) /* Window 2 buffer start address register */
-#define S5P_VIDW03ADD0 S5P_LCDREG(0x0B8) /* Window 3 buffer start address register */
-#define S5P_VIDW04ADD0 S5P_LCDREG(0x0C0) /* Window 4 buffer start address register */
-#define S5P_VIDW00ADD1B0 S5P_LCDREG(0x0D0) /* Window 0 buffer end address register, buffer 0 */
-#define S5P_VIDW00ADD1B1 S5P_LCDREG(0x0D4) /* Window 0 buffer end address register, buffer 1 */
-#define S5P_VIDW01ADD1B0 S5P_LCDREG(0x0D8) /* Window 1 buffer end address register, buffer 0 */
-#define S5P_VIDW01ADD1B1 S5P_LCDREG(0x0DC) /* Window 1 buffer end address register, buffer 1 */
-#define S5P_VIDW02ADD1 S5P_LCDREG(0x0E0) /* Window 2 buffer end address register */
-#define S5P_VIDW03ADD1 S5P_LCDREG(0x0E8) /* Window 3 buffer end address register */
-#define S5P_VIDW04ADD1 S5P_LCDREG(0x0F0) /* Window 4 buffer end address register */
-#define S5P_VIDW00ADD2 S5P_LCDREG(0x100) /* Window 0 buffer size register */
-#define S5P_VIDW01ADD2 S5P_LCDREG(0x104) /* Window 1 buffer size register */
-
-#define S5P_VIDW02ADD2 S5P_LCDREG(0x108) /* Window 2 buffer size register */
-#define S5P_VIDW03ADD2 S5P_LCDREG(0x10C) /* Window 3 buffer size register */
-#define S5P_VIDW04ADD2 S5P_LCDREG(0x110) /* Window 4 buffer size register */
-
-#define S5P_VIDINTCON0 S5P_LCDREG(0x130) /* Indicate the Video interrupt control register */
-#define S5P_VIDINTCON1 S5P_LCDREG(0x134) /* Video Interrupt Pending register */
-#define S5P_W1KEYCON0 S5P_LCDREG(0x140) /* Color key control register */
-#define S5P_W1KEYCON1 S5P_LCDREG(0x144) /* Color key value ( transparent value) register */
-#define S5P_W2KEYCON0 S5P_LCDREG(0x148) /* Color key control register */
-#define S5P_W2KEYCON1 S5P_LCDREG(0x14C) /* Color key value (transparent value) register */
-
-#define S5P_W3KEYCON0 S5P_LCDREG(0x150) /* Color key control register */
-#define S5P_W3KEYCON1 S5P_LCDREG(0x154) /* Color key value (transparent value) register */
-#define S5P_W4KEYCON0 S5P_LCDREG(0x158) /* Color key control register */
-#define S5P_W4KEYCON1 S5P_LCDREG(0x15C) /* Color key value (transparent value) register */
-#define S5P_DITHMODE S5P_LCDREG(0x170) /* Dithering mode register. */
-
-#define S5P_WIN0MAP S5P_LCDREG(0x180) /* Window color control */
-#define S5P_WIN1MAP S5P_LCDREG(0x184) /* Window color control */
-#define S5P_WIN2MAP S5P_LCDREG(0x188) /* Window color control */
-#define S5P_WIN3MAP S5P_LCDREG(0x18C) /* Window color control */
-#define S5P_WIN4MAP S5P_LCDREG(0x190) /* Window color control */
-#define S5P_WPALCON S5P_LCDREG(0x1A0) /* Window Palette control register */
-
-#define S5P_TRIGCON S5P_LCDREG(0x1A4) /* I80 / RGB Trigger Control Regiter */
-#define S5P_I80IFCONA0 S5P_LCDREG(0x1B0) /* I80 Interface control 0 for Main LDI */
-#define S5P_I80IFCONA1 S5P_LCDREG(0x1B4) /* I80 Interface control 0 for Sub LDI */
-#define S5P_I80IFCONB0 S5P_LCDREG(0x1B8) /* I80 Inteface control 1 for Main LDI */
-#define S5P_I80IFCONB1 S5P_LCDREG(0x1BC) /* I80 Inteface control 1 for Sub LDI */
-#define S5P_LDI_CMDCON0 S5P_LCDREG(0x1D0) /* I80 Interface LDI Command Control 0 */
-#define S5P_LDI_CMDCON1 S5P_LCDREG(0x1D4) /* I80 Interface LDI Command Control 1 */
-#define S5P_SIFCCON0 S5P_LCDREG(0x1E0) /* LCD i80 System Interface Command Control 0 */
-#define S5P_SIFCCON1 S5P_LCDREG(0x1E4) /* LCD i80 System Interface Command Control 1 */
-#define S5P_SIFCCON2 S5P_LCDREG(0x1E8) /* LCD i80 System Interface Command Control 2 */
-
-#define S5P_LDI_CMD0 S5P_LCDREG(0x280) /* I80 Inteface LDI Command 0 */
-#define S5P_LDI_CMD1 S5P_LCDREG(0x284) /* I80 Inteface LDI Command 1 */
-#define S5P_LDI_CMD2 S5P_LCDREG(0x288) /* I80 Inteface LDI Command 2 */
-#define S5P_LDI_CMD3 S5P_LCDREG(0x28C) /* I80 Inteface LDI Command 3 */
-#define S5P_LDI_CMD4 S5P_LCDREG(0x290) /* I80 Inteface LDI Command 4 */
-#define S5P_LDI_CMD5 S5P_LCDREG(0x294) /* I80 Inteface LDI Command 5 */
-#define S5P_LDI_CMD6 S5P_LCDREG(0x298) /* I80 Inteface LDI Command 6 */
-#define S5P_LDI_CMD7 S5P_LCDREG(0x29C) /* I80 Inteface LDI Command 7 */
-#define S5P_LDI_CMD8 S5P_LCDREG(0x2A0) /* I80 Inteface LDI Command 8 */
-#define S5P_LDI_CMD9 S5P_LCDREG(0x2A4) /* I80 Inteface LDI Command 9 */
-#define S5P_LDI_CMD10 S5P_LCDREG(0x2A8) /* I80 Inteface LDI Command 10 */
-#define S5P_LDI_CMD11 S5P_LCDREG(0x2AC) /* I80 Inteface LDI Command 11 */
-
-#define S5P_W2PDATA01 S5P_LCDREG(0x300) /* Window 2 Palette Data of the Index 0,1 */
-#define S5P_W2PDATA23 S5P_LCDREG(0x304) /* Window 2 Palette Data of the Index 2,3 */
-#define S5P_W2PDATA45 S5P_LCDREG(0x308) /* Window 2 Palette Data of the Index 4,5 */
-#define S5P_W2PDATA67 S5P_LCDREG(0x30C) /* Window 2 Palette Data of the Index 6,7 */
-#define S5P_W2PDATA89 S5P_LCDREG(0x310) /* Window 2 Palette Data of the Index 8,9 */
-#define S5P_W2PDATAAB S5P_LCDREG(0x314) /* Window 2 Palette Data of the Index A, B */
-#define S5P_W2PDATACD S5P_LCDREG(0x318) /* Window 2 Palette Data of the Index C, D */
-#define S5P_W2PDATAEF S5P_LCDREG(0x31C) /* Window 2 Palette Data of the Index E, F */
-#define S5P_W3PDATA01 S5P_LCDREG(0x320) /* Window 3 Palette Data of the Index 0,1 */
-#define S5P_W3PDATA23 S5P_LCDREG(0x324) /* Window 3 Palette Data of the Index 2,3 */
-#define S5P_W3PDATA45 S5P_LCDREG(0x328) /* Window 3 Palette Data of the Index 4,5 */
-#define S5P_W3PDATA67 S5P_LCDREG(0x32C) /* Window 3 Palette Data of the Index 6,7 */
-#define S5P_W3PDATA89 S5P_LCDREG(0x330) /* Window 3 Palette Data of the Index 8,9 */
-#define S5P_W3PDATAAB S5P_LCDREG(0x334) /* Window 3 Palette Data of the Index A, B */
-#define S5P_W3PDATACD S5P_LCDREG(0x338) /* Window 3 Palette Data of the Index C, D */
-#define S5P_W3PDATAEF S5P_LCDREG(0x33C) /* Window 3 Palette Data of the Index E, F */
-#define S5P_W4PDATA01 S5P_LCDREG(0x340) /* Window 3 Palette Data of the Index 0,1 */
-#define S5P_W4PDATA23 S5P_LCDREG(0x344) /* Window 3 Palette Data of the Index 2,3 */
-
-#define S5P_TFTPAL2(x) S5P_LCDREG((0x300 + (x)*4))
-#define S5P_TFTPAL3(x) S5P_LCDREG((0x320 + (x)*4))
-#define S5P_TFTPAL4(x) S5P_LCDREG((0x340 + (x)*4))
-#define S5P_TFTPAL0(x) S5P_LCDREG((0x400 + (x)*4))
-#define S5P_TFTPAL1(x) S5P_LCDREG((0x800 + (x)*4))
-
-/*--------------------------------------------------------------*/
-/* Video Main Control 0 register - VIDCON0 */
-#define S5P_VIDCON0_INTERLACE_F_PROGRESSIVE (0<<29)
-#define S5P_VIDCON0_INTERLACE_F_INTERLACE (1<<29)
-#define S5P_VIDCON0_INTERLACE_F_MASK (1<<29)
-#define S5P_VIDCON0_VIDOUT(x) (((x)&0x7)<<26)
-#define S5P_VIDCON0_VIDOUT_RGB_IF (0<<26)
-#define S5P_VIDCON0_VIDOUT_TV (1<<26)
-#define S5P_VIDCON0_VIDOUT_I80IF0 (2<<26)
-#define S5P_VIDCON0_VIDOUT_I80IF1 (3<<26)
-#define S5P_VIDCON0_VIDOUT_TVNRGBIF (4<<26)
-#define S5P_VIDCON0_VIDOUT_TVNI80IF0 (6<<26)
-#define S5P_VIDCON0_VIDOUT_TVNI80IF1 (7<<26)
-#define S5P_VIDCON0_VIDOUT_MASK (7<<26)
-#define S5P_VIDCON0_L1_DATA16(x) (((x)&0x7)<<23)
-#define S5P_VIDCON0_L1_DATA16_SUB_16_MODE (0<<23)
-#define S5P_VIDCON0_L1_DATA16_SUB_16PLUS2_MODE (1<<23)
-#define S5P_VIDCON0_L1_DATA16_SUB_9PLUS9_MODE (2<<23)
-#define S5P_VIDCON0_L1_DATA16_SUB_16PLUS8_MODE (3<<23)
-#define S5P_VIDCON0_L1_DATA16_SUB_18_MODE (4<<23)
-#define S5P_VIDCON0_L0_DATA16(x) (((x)&0x7)<<20)
-#define S5P_VIDCON0_L0_DATA16_MAIN_16_MODE (0<<20)
-#define S5P_VIDCON0_L0_DATA16_MAIN_16PLUS2_MODE (1<<20)
-#define S5P_VIDCON0_L0_DATA16_MAIN_9PLUS9_MODE (2<<20)
-#define S5P_VIDCON0_L0_DATA16_MAIN_16PLUS8_MODE (3<<20)
-#define S5P_VIDCON0_L0_DATA16_MAIN_18_MODE (4<<20)
-#define S5P_VIDCON0_PNRMODE(x) (((x)&0x3)<<17)
-#define S5P_VIDCON0_PNRMODE_RGB_P (0<<17)
-#define S5P_VIDCON0_PNRMODE_BGR_P (1<<17)
-#define S5P_VIDCON0_PNRMODE_RGB_S (2<<17)
-#define S5P_VIDCON0_PNRMODE_BGR_S (3<<17)
-#define S5P_VIDCON0_PNRMODE_MASK (3<<17)
-#define S5P_VIDCON0_CLKVALUP_ALWAYS (0<<16)
-#define S5P_VIDCON0_CLKVALUP_ST_FRM (1<<16)
-#define S5P_VIDCON0_CLKVAL_F(x) (((x)&0xFF)<<6)
-#define S5P_VIDCON0_VCLKEN_ENABLE (1<<5)
-#define S5P_VIDCON0_CLKDIR_DIVIDED (1<<4)
-#define S5P_VIDCON0_CLKDIR_DIRECTED (0<<4)
-#define S5P_VIDCON0_CLKSEL(x) (((x)&0x3)<<2)
-#define S5P_VIDCON0_CLKSEL_F_HCLK (0<<2)
-#define S5P_VIDCON0_ENVID_ENABLE (1 << 1) /* 0:Disable 1:Enable LCD video output and logic immediatly */
-#define S5P_VIDCON0_ENVID_DISABLE (0 << 1) /* 0:Disable 1:Enable LCD video output and logic immediatly */
-#define S5P_VIDCON0_ENVID_F_ENABLE (1 << 0) /* 0:Dis 1:Ena wait until Current frame end. */
-#define S5P_VIDCON0_ENVID_F_DISABLE (0 << 0) /* 0:Dis 1:Ena wait until Current frame end. */
-
-/* Video Main Control 1 register - VIDCON1 */
-#define S5P_VIDCON1_IVCLK_FALL_EDGE (0<<7)
-#define S5P_VIDCON1_IVCLK_RISE_EDGE (1<<7)
-#define S5P_VIDCON1_IHSYNC_NORMAL (0<<6)
-#define S5P_VIDCON1_IHSYNC_INVERT (1<<6)
-#define S5P_VIDCON1_IVSYNC_NORMAL (0<<5)
-#define S5P_VIDCON1_IVSYNC_INVERT (1<<5)
-#define S5P_VIDCON1_IVDEN_NORMAL (0<<4)
-#define S5P_VIDCON1_IVDEN_INVERT (1<<4)
-
-/* Video Main Control 2 register - VIDCON2 */
-#define S5P_VIDCON2_EN601_DISABLE (0<<23)
-#define S5P_VIDCON2_EN601_ENABLE (1<<23)
-#define S5P_VIDCON2_EN601_MASK (1<<23)
-#define S5P_VIDCON2_TVFORMATSEL0_HARDWARE (0<<14)
-#define S5P_VIDCON2_TVFORMATSEL0_SOFTWARE (1<<14)
-#define S5P_VIDCON2_TVFORMATSEL0_MASK (1<<14)
-#define S5P_VIDCON2_TVFORMATSEL1_RGB (0<<12)
-#define S5P_VIDCON2_TVFORMATSEL1_YUV422 (1<<12)
-#define S5P_VIDCON2_TVFORMATSEL1_YUV444 (2<<12)
-#define S5P_VIDCON2_TVFORMATSEL1_MASK (0x3<<12)
-#define S5P_VIDCON2_ORGYUV_YCBCR (0<<8)
-#define S5P_VIDCON2_ORGYUV_CBCRY (1<<8)
-#define S5P_VIDCON2_ORGYUV_MASK (1<<8)
-#define S5P_VIDCON2_YUVORD_CBCR (0<<7)
-#define S5P_VIDCON2_YUVORD_CRCB (1<<7)
-#define S5P_VIDCON2_YUVORD_MASK (1<<7)
-
-/* VIDEO Time Control 0 register - VIDTCON0 */
-#define S5P_VIDTCON0_VBPDE(x) (((x)&0xFF)<<24)
-#define S5P_VIDTCON0_VBPD(x) (((x)&0xFF)<<16)
-#define S5P_VIDTCON0_VFPD(x) (((x)&0xFF)<<8)
-#define S5P_VIDTCON0_VSPW(x) (((x)&0xFF)<<0)
-
-/* VIDEO Time Control 1 register - VIDTCON1 */
-#define S5P_VIDTCON1_VFPDE(x) (((x)&0xFF)<<24)
-#define S5P_VIDTCON1_HBPD(x) (((x)&0xFF)<<16)
-#define S5P_VIDTCON1_HFPD(x) (((x)&0xFF)<<8)
-#define S5P_VIDTCON1_HSPW(x) (((x)&0xFF)<<0)
-
-/* VIDEO Time Control 2 register - VIDTCON2 */
-#define S5P_VIDTCON2_LINEVAL(x) (((x)&0x7FF)<<11) /* these bits determine the vertical size of lcd panel */
-#define S5P_VIDTCON2_HOZVAL(x) (((x)&0x7FF)<<0) /* these bits determine the horizontal size of lcd panel*/
-
-
-/* Window 0~4 Control register - WINCONx */
-#define S5P_WINCONx_WIDE_NARROW(x) (((x)&0x3)<<26)
-#define S5P_WINCONx_ENLOCAL_DMA (0<<22)
-#define S5P_WINCONx_ENLOCAL (1<<22)
-#define S5P_WINCONx_ENLOCAL_MASK (1<<22)
-#define S5P_WINCONx_BUFSEL_0 (0<<20)
-#define S5P_WINCONx_BUFSEL_1 (1<<20)
-#define S5P_WINCONx_BUFSEL_MASK (1<<20)
-#define S5P_WINCONx_BUFAUTOEN_DISABLE (0<<19)
-#define S5P_WINCONx_BUFAUTOEN_ENABLE (1<<19)
-#define S5P_WINCONx_BUFAUTOEN_MASK (1<<19)
-#define S5P_WINCONx_BITSWP_DISABLE (0<<18)
-#define S5P_WINCONx_BITSWP_ENABLE (1<<18)
-#define S5P_WINCONx_BYTSWP_DISABLE (0<<17)
-#define S5P_WINCONx_BYTSWP_ENABLE (1<<17)
-#define S5P_WINCONx_HAWSWP_DISABLE (0<<16)
-#define S5P_WINCONx_HAWSWP_ENABLE (1<<16)
-#define S5P_WINCONx_WSWP_DISABLE (0<<15)
-#define S5P_WINCONx_WSWP_ENABLE (1<<15)
-#define S5P_WINCONx_INRGB_RGB (0<<13)
-#define S5P_WINCONx_INRGB_YUV (1<<13)
-#define S5P_WINCONx_INRGB_MASK (1<<13)
-#define S5P_WINCONx_BURSTLEN_16WORD (0<<9)
-#define S5P_WINCONx_BURSTLEN_8WORD (1<<9)
-#define S5P_WINCONx_BURSTLEN_4WORD (2<<9)
-#define S5P_WINCONx_BLD_PIX_PLANE (0<<6)
-#define S5P_WINCONx_BLD_PIX_PIXEL (1<<6)
-#define S5P_WINCONx_BLD_PIX_MASK (1<<6)
-#define S5P_WINCONx_BPPMODE_F_1BPP (0<<2)
-#define S5P_WINCONx_BPPMODE_F_2BPP (1<<2)
-#define S5P_WINCONx_BPPMODE_F_4BPP (2<<2)
-#define S5P_WINCONx_BPPMODE_F_8BPP_PAL (3<<2)
-#define S5P_WINCONx_BPPMODE_F_8BPP_NOPAL (4<<2)
-#define S5P_WINCONx_BPPMODE_F_16BPP_565 (5<<2)
-#define S5P_WINCONx_BPPMODE_F_16BPP_A555 (6<<2)
-#define S5P_WINCONx_BPPMODE_F_18BPP_666 (8<<2)
-#define S5P_WINCONx_BPPMODE_F_24BPP_888 (11<<2)
-#define S5P_WINCONx_BPPMODE_F_24BPP_A887 (0xc<<2)
-#define S5P_WINCONx_BPPMODE_F_25BPP_A888 (0xd<<2)
-#define S5P_WINCONx_BPPMODE_F_28BPP_A888 (0xd<<2)
-#define S5P_WINCONx_BPPMODE_F_MASK (0xf<<2)
-#define S5P_WINCONx_ALPHA_SEL_0 (0<<1)
-#define S5P_WINCONx_ALPHA_SEL_1 (1<<1)
-#define S5P_WINCONx_ALPHA_SEL_MASK (1<<1)
-#define S5P_WINCONx_ENWIN_F_DISABLE (0<<0)
-#define S5P_WINCONx_ENWIN_F_ENABLE (1<<0)
-
-/* Window 1-2 Control register - WINCON1 */
-#define S5P_WINCON1_LOCALSEL_TV (0<<23)
-#define S5P_WINCON1_LOCALSEL_CAMERA (1<<23)
-#define S5P_WINCON1_LOCALSEL_MASK (1<<23)
-#define S5P_WINCON2_LOCALSEL_TV (0<<23)
-#define S5P_WINCON2_LOCALSEL_CAMERA (1<<23)
-#define S5P_WINCON2_LOCALSEL_MASK (1<<23)
-
-/* Window 0~4 Position Control A register - VIDOSDxA */
-#define S5P_VIDOSDxA_OSD_LTX_F(x) (((x)&0x7FF)<<11)
-#define S5P_VIDOSDxA_OSD_LTY_F(x) (((x)&0x7FF)<<0)
-
-/* Window 0~4 Position Control B register - VIDOSDxB */
-#define S5P_VIDOSDxB_OSD_RBX_F(x) (((x)&0x7FF)<<11)
-#define S5P_VIDOSDxB_OSD_RBY_F(x) (((x)&0x7FF)<<0)
-
-/* Window 0 Position Control C register - VIDOSD0C */
-#define S5P_VIDOSD0C_OSDSIZE(x) (((x)&0xFFFFFF)<<0)
-
-/* Window 1~4 Position Control C register - VIDOSDxC */
-#define S5P_VIDOSDxC_ALPHA0_R(x) (((x)&0xF)<<20)
-#define S5P_VIDOSDxC_ALPHA0_G(x) (((x)&0xF)<<16)
-#define S5P_VIDOSDxC_ALPHA0_B(x) (((x)&0xF)<<12)
-#define S5P_VIDOSDxC_ALPHA1_R(x) (((x)&0xF)<<8)
-#define S5P_VIDOSDxC_ALPHA1_G(x) (((x)&0xF)<<4)
-#define S5P_VIDOSDxC_ALPHA1_B(x) (((x)&0xF)<<0)
-
-/* Window 1~2 Position Control D register - VIDOSDxD */
-#define S5P_VIDOSDxD_OSDSIZE(x) (((x)&0xFFFFFF)<<0)
-
-/* Frame buffer Start Address register - VIDWxxADD0 */
-#define S5P_VIDWxxADD0_VBANK_F(x) (((x)&0xFF)<<23) /* the end address of the LCD frame buffer. */
-#define S5P_VIDWxxADD0_VBASEU_F(x) (((x)&0xFFFFFF)<<0) /* Virtual screen offset size (the number of byte). */
-
-/* Frame buffer End Address register - VIDWxxADD1 */
-#define S5P_VIDWxxADD1_VBASEL_F(x) (((x)&0xFFFFFF)<<0) /* the end address of the LCD frame buffer. */
-
-/* Frame buffer Size register - VIDWxxADD2 */
-#define S5P_VIDWxxADD2_OFFSIZE_F(x) (((x)&0x1FFF)<<13) /* Virtual screen offset size (the number of byte). */
-#define S5P_VIDWxxADD2_PAGEWIDTH_F(x) (((x)&0x1FFF)<<0) /* Virtual screen page width (the number of byte). */
-
-/* VIDEO Interrupt Control 0 register - VIDINTCON0 */
-#define S5P_VIDINTCON0_FIFOINTERVAL(x) (((x)&0x3F)<<20)
-#define S5P_VIDINTCON0_SYSMAINCON_DISABLE (0<<19)
-#define S5P_VIDINTCON0_SYSMAINCON_ENABLE (1<<19)
-#define S5P_VIDINTCON0_SYSSUBCON_DISABLE (0<<18)
-#define S5P_VIDINTCON0_SYSSUBCON_ENABLE (1<<18)
-#define S5P_VIDINTCON0_SYSIFDONE_DISABLE (0<<17)
-#define S5P_VIDINTCON0_SYSIFDONE_ENABLE (1<<17)
-#define S5P_VIDINTCON0_FRAMESEL0_BACK (0<<15)
-#define S5P_VIDINTCON0_FRAMESEL0_VSYNC (1<<15)
-#define S5P_VIDINTCON0_FRAMESEL0_ACTIVE (2<<15)
-#define S5P_VIDINTCON0_FRAMESEL0_FRONT (3<<15)
-#define S5P_VIDINTCON0_FRAMESEL0_MASK (3<<15)
-#define S5P_VIDINTCON0_FRAMESEL1_NONE (0<<13)
-#define S5P_VIDINTCON0_FRAMESEL1_BACK (1<<13)
-#define S5P_VIDINTCON0_FRAMESEL1_VSYNC (2<<13)
-#define S5P_VIDINTCON0_FRAMESEL1_FRONT (3<<13)
-#define S5P_VIDINTCON0_INTFRMEN_DISABLE (0<<12)
-#define S5P_VIDINTCON0_INTFRMEN_ENABLE (1<<12)
-#define S5P_VIDINTCON0_FRAMEINT_MASK (0x1F<<12)
-#define S5P_VIDINTCON0_FIFOSEL_WIN4 (1<<11)
-#define S5P_VIDINTCON0_FIFOSEL_WIN3 (1<<10)
-#define S5P_VIDINTCON0_FIFOSEL_WIN2 (1<<9)
-#define S5P_VIDINTCON0_FIFOSEL_WIN1 (1<<6)
-#define S5P_VIDINTCON0_FIFOSEL_WIN0 (1<<5)
-#define S5P_VIDINTCON0_FIFOSEL_ALL (0x73<<5)
-#define S5P_VIDINTCON0_FIFOLEVEL_25 (0<<2)
-#define S5P_VIDINTCON0_FIFOLEVEL_50 (1<<2)
-#define S5P_VIDINTCON0_FIFOLEVEL_75 (2<<2)
-#define S5P_VIDINTCON0_FIFOLEVEL_EMPTY (3<<2)
-#define S5P_VIDINTCON0_FIFOLEVEL_FULL (4<<2)
-#define S5P_VIDINTCON0_INTFIFOEN_DISABLE (0<<1)
-#define S5P_VIDINTCON0_INTFIFOEN_ENABLE (1<<1)
-#define S5P_VIDINTCON0_INTEN_DISABLE (0<<0)
-#define S5P_VIDINTCON0_INTEN_ENABLE (1<<0)
-#define S5P_VIDINTCON0_INTEN_MASK (1<<0)
-
-/* VIDEO Interrupt Control 1 register - VIDINTCON1 */
-#define S5P_VIDINTCON1_INTI80PEND (0<<2)
-#define S5P_VIDINTCON1_INTFRMPEND (1<<1)
-#define S5P_VIDINTCON1_INTFIFOPEND (1<<0)
-
-/* WIN 1~4 Color Key 0 register - WxKEYCON0 */
-#define S5P_WxKEYCON0_KEYBLEN_DISABLE (0<<26)
-#define S5P_WxKEYCON0_KEYBLEN_ENABLE (1<<26)
-#define S5P_WxKEYCON0_KEYEN_F_DISABLE (0<<25)
-#define S5P_WxKEYCON0_KEYEN_F_ENABLE (1<<25)
-#define S5P_WxKEYCON0_DIRCON_MATCH_FG_IMAGE (0<<24)
-#define S5P_WxKEYCON0_DIRCON_MATCH_BG_IMAGE (1<<24)
-#define S5P_WxKEYCON0_COMPKEY(x) (((x)&0xFFFFFF)<<0)
-
-/* WIN 1~4 Color Key 1 register - WxKEYCON1 */
-#define S5P_WxKEYCON1_COLVAL(x) (((x)&0xFFFFFF)<<0)
-
-/* Dithering Control 1 register - DITHMODE */
-#define S5P_DITHMODE_RDITHPOS_8BIT (0<<5)
-#define S5P_DITHMODE_RDITHPOS_6BIT (1<<5)
-#define S5P_DITHMODE_RDITHPOS_5BIT (2<<5)
-#define S5P_DITHMODE_GDITHPOS_8BIT (0<<3)
-#define S5P_DITHMODE_GDITHPOS_6BIT (1<<3)
-#define S5P_DITHMODE_GDITHPOS_5BIT (2<<3)
-#define S5P_DITHMODE_BDITHPOS_8BIT (0<<1)
-#define S5P_DITHMODE_BDITHPOS_6BIT (1<<1)
-#define S5P_DITHMODE_BDITHPOS_5BIT (2<<1)
-#define S5P_DITHMODE_RGB_DITHPOS_MASK (0x3f<<1)
-#define S5P_DITHMODE_DITHERING_DISABLE (0<<0)
-#define S5P_DITHMODE_DITHERING_ENABLE (1<<0)
-#define S5P_DITHMODE_DITHERING_MASK (1<<0)
-
-/* Window 0~4 Color map register - WINxMAP */
-#define S5P_WINxMAP_MAPCOLEN_F_ENABLE (1<<24)
-#define S5P_WINxMAP_MAPCOLEN_F_DISABLE (0<<24)
-#define S5P_WINxMAP_MAPCOLOR (((x)&0xFFFFFF)<<0)
-
-/* Window Palette Control register - WPALCON */
-#define S5P_WPALCON_PALUPDATEEN (1<<9)
-#define S5P_WPALCON_W4PAL_16BIT_A (1<<8) /* A:5:5:5 */
-#define S5P_WPALCON_W4PAL_16BIT (0<<8) /* 5:6:5 */
-#define S5P_WPALCON_W3PAL_16BIT_A (1<<7) /* A:5:5:5 */
-#define S5P_WPALCON_W3PAL_16BIT (0<<7) /* 5:6:5 */
-#define S5P_WPALCON_W2PAL_16BIT_A (1<<6) /* A:5:5:5 */
-#define S5P_WPALCON_W2PAL_16BIT (0<<6) /* 5:6:5 */
-#define S5P_WPALCON_W1PAL_25BIT_A (0<<3) /* A:8:8:8 */
-#define S5P_WPALCON_W1PAL_24BIT (1<<3) /* 8:8:8 */
-#define S5P_WPALCON_W1PAL_19BIT_A (2<<3) /* A:6:6:6 */
-#define S5P_WPALCON_W1PAL_18BIT_A (3<<3) /* A:6:6:5 */
-#define S5P_WPALCON_W1PAL_18BIT (4<<3) /* 6:6:6 */
-#define S5P_WPALCON_W1PAL_16BIT_A (5<<3) /* A:5:5:5 */
-#define S5P_WPALCON_W1PAL_16BIT (6<<3) /* 5:6:5 */
-#define S5P_WPALCON_W0PAL_25BIT_A (0<<0) /* A:8:8:8 */
-#define S5P_WPALCON_W0PAL_24BIT (1<<0) /* 8:8:8 */
-#define S5P_WPALCON_W0PAL_19BIT_A (2<<0) /* A:6:6:6 */
-#define S5P_WPALCON_W0PAL_18BIT_A (3<<0) /* A:6:6:5 */
-#define S5P_WPALCON_W0PAL_18BIT (4<<0) /* 6:6:6 */
-#define S5P_WPALCON_W0PAL_16BIT_A (5<<0) /* A:5:5:5 */
-#define S5P_WPALCON_W0PAL_16BIT (6<<0) /* 5:6:5 */
-
-/* I80/RGB Trigger Control register - TRIGCON */
-#define S5P_TRIGCON_SWFRSTATUS_REQUESTED (1<<2)
-#define S5P_TRIGCON_SWFRSTATUS_NOT_REQUESTED (0<<2)
-#define S5P_TRIGCON_SWTRGCMD (1<<1)
-#define S5P_TRIGCON_TRGMODE_ENABLE (1<<0)
-#define S5P_TRIGCON_TRGMODE_DISABLE (0<<0)
-
-/* LCD I80 Interface Control 0 register - I80IFCONA0 */
-#define S5P_I80IFCONAx_LCD_CS_SETUP(x) (((x)&0xF)<<16)
-#define S5P_I80IFCONAx_LCD_WR_SETUP(x) (((x)&0xF)<<12)
-#define S5P_I80IFCONAx_LCD_WR_ACT(x) (((x)&0xF)<<8)
-#define S5P_I80IFCONAx_LCD_WR_HOLD(x) (((x)&0xF)<<4)
-
-
-/***************************************************************************/
-/*HOST IF registers */
-/* Host I/F A - */
-#define S5P_HOSTIFAREG(x) ((x) + S5PC64XX_VA_HOSTIFA)
-#define S5P_HOSTIFAREG_PHYS(x) ((x) + S5PC64XX_PA_HOSTIFA)
-
-/* Host I/F B - Modem I/F */
-#define S5P_HOSTIFBREG(x) ((x) + S5PC64XX_VA_HOSTIFB)
-#define S5P_HOSTIFBREG_PHYS(x) ((x) + S5PC64XX_PA_HOSTIFB)
-
-#define S5P_HOSTIFB_INT2AP S5P_HOSTIFBREG(0x8000)
-#define S5P_HOSTIFB_INT2MSM S5P_HOSTIFBREG(0x8004)
-#define S5P_HOSTIFB_MIFCON S5P_HOSTIFBREG(0x8008)
-#define S5P_HOSTIFB_MIFPCON S5P_HOSTIFBREG(0x800C)
-#define S5P_HOSTIFB_MSMINTCLR S5P_HOSTIFBREG(0x8010)
-
-#define S5P_HOSTIFB_MIFCON_INT2MSM_DIS (0x0<<3)
-#define S5P_HOSTIFB_MIFCON_INT2MSM_EN (0x1<<3)
-#define S5P_HOSTIFB_MIFCON_INT2AP_DIS (0x0<<2)
-#define S5P_HOSTIFB_MIFCON_INT2AP_EN (0x1<<2)
-#define S5P_HOSTIFB_MIFCON_WAKEUP_DIS (0x0<<1)
-#define S5P_HOSTIFB_MIFCON_WAKEUP_EN (0x1<<1)
-
-#define S5P_HOSTIFB_MIFPCON_SEL_VSYNC_DIR_OUT (0x0<<5)
-#define S5P_HOSTIFB_MIFPCON_SEL_VSYNC_DIR_IN (0x1<<5)
-#define S5P_HOSTIFB_MIFPCON_INT2M_LEVEL_DIS (0x0<<4)
-#define S5P_HOSTIFB_MIFPCON_INT2M_LEVEL_EN (0x1<<4)
-#define S5P_HOSTIFB_MIFPCON_SEL_NORMAL (0x0<<3)
-#define S5P_HOSTIFB_MIFPCON_SEL_BYPASS (0x1<<3)
-
-#define S5P_HOSTIFB_MIFPCON_SEL_RS0 0
-#define S5P_HOSTIFB_MIFPCON_SEL_RS1 1
-#define S5P_HOSTIFB_MIFPCON_SEL_RS2 2
-#define S5P_HOSTIFB_MIFPCON_SEL_RS3 3
-#define S5P_HOSTIFB_MIFPCON_SEL_RS4 4
-#define S5P_HOSTIFB_MIFPCON_SEL_RS5 5
-#define S5P_HOSTIFB_MIFPCON_SEL_RS6 6
-
-#define S5P_WINCONx_ENLOCAL_POST (1<<22)
-#endif
projects / kernel / u-boot.git / commitdiff