drm/amdgpu: fix aper_base for APU
authorRoman Li <Roman.Li@amd.com>
Wed, 25 May 2022 21:20:21 +0000 (17:20 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Jun 2022 19:56:59 +0000 (15:56 -0400)
[Why]
Wrong fb offset results in dmub f/w errors and white screen.
[drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3

[How]
Read aper_base from mmhub because GC is off by default

v2: use BAR for passthrough (Alex)

Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

index a0c0b7d..7f4b480 100644 (file)
@@ -638,6 +638,12 @@ static int gmc_v11_0_mc_init(struct amdgpu_device *adev)
        adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
        adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 
+#ifdef CONFIG_X86_64
+       if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
+               adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev);
+               adev->gmc.aper_size = adev->gmc.real_vram_size;
+       }
+#endif
        /* In case the PCI BAR is larger than the actual amount of vram */
        adev->gmc.visible_vram_size = adev->gmc.aper_size;
        if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)